From ddbf946f7b5251bf9106dcbd1166801dffd290e7 Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson <stefank@nvidia.com> Date: Mon, 20 Mar 2017 14:19:46 +0200 Subject: [PATCH] Tegra194: Fix TEGRA186_SMMU_CTX_SIZE TEGRA186_SMMU_CTX_SIZE should match the numbe of elements in smmu_ctx_regs, which is defined in smmu_plat_config.h. The current number of elements are 0x490. Change-Id: If0614ea8ef8b6a8f5da1a3279abaf9255eb76420 Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> --- plat/nvidia/tegra/soc/t194/plat_trampoline.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index cf765076a..e3ee5e5a5 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -10,7 +10,7 @@ #include <memctrl_v2.h> #include <tegra_def.h> -#define TEGRA186_SMMU_CTX_SIZE 0x420 +#define TEGRA186_SMMU_CTX_SIZE 0x490 .align 4 .globl tegra186_cpu_reset_handler @@ -56,12 +56,12 @@ boot_cpu: endfunc tegra186_cpu_reset_handler /* - * Tegra186 reset data (offset 0x0 - 0x430) + * Tegra186 reset data (offset 0x0 - 0x2490) * - * 0x000: secure world's entrypoint - * 0x008: BL31 size (RO + RW) - * 0x00C: SMMU context start - * 0x42C: SMMU context end + * 0x0000: secure world's entrypoint + * 0x0008: BL31 size (RO + RW) + * 0x0010: SMMU context start + * 0x2490: SMMU context end */ .align 4 -- GitLab