Merge changes from topic "jun-add-imx7-pico" into integration

* changes:
  plat: imx7: Add PicoPi iMX7D basic support
  plat: imx7: refactor code for reuse

plat/imx/common/include/imx_clock.h

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef IMX_CLOCK_H
@@ -819,6 +818,8 @@ struct ccm_target_root_ctrl {
 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_USB_PLL			(BIT(26) | BIT(24))
 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD1_DIV2		((BIT(26) | BIT(25) | BIT(24))
+#define WDOG_DEFAULT_CLK_SELECT					(CCM_TARGET_ROOT_ENABLE |\
+								CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
 
 /* Target CSI_MCLK_CLK_ROOT */
 

plat/imx/common/include/imx_io_mux.h

 /*
- * Copyright 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #define IMX_IO_MUX_H
 
 #include <stdint.h>
+#include <lib/utils_def.h>
 
 /*
  * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
@@ -20,7 +21,10 @@
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET		0x0020
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET		0x0024
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET		0x0028
+
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET		0x002C
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B	BIT(0)
+
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET		0x0030
 
 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET	0x0034
@@ -121,8 +125,24 @@
 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET		0x0154
 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET		0x0158
 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET		0x015C
+
 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET		0x0160
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT0_I2C4_SCL		0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA	BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT2_WDOG4_WDOG_B	BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT3_CSI_PIXCLK		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT4_USB_OTG1_ID		BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT5_GPIO4_IO14		(BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT6_EPDC_VCOM0		(BIT(2) | BIT(1))
+
 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET		0x0164
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT0_I2C4_SDA		0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA	BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT2_WDOG4_WDOG_RST_B_DEB BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT3_CSI_MCLK		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT4_USB_OTG2_ID		BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT5_GPIO4_IO15		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT6_EPDC_VCOM1		(BIT(2) | BIT(1))
 
 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET	0x0168
 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK	0x00
@@ -165,6 +185,7 @@
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET		0x01C4
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET		0x01C8
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET		0x01CC
+
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET		0x01D0
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET		0x01D4
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET		0x01D8
@@ -391,6 +412,7 @@
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET		0x0434
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET		0x0438
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET		0x043C
+
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET		0x0440
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET		0x0444
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET		0x0448
@@ -403,6 +425,19 @@
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET		0x0464
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET		0x0468
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET	0x046C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_0_X1		0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4		BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_2_X2		BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6		(BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4		BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW		BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_FAST		0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_HYS			BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PE			BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PD_100K		(0 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_5K			(1 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K		(2 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_100K		(3 << 5)
 
 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET	0x0470
 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET	0x0474
@@ -588,7 +623,15 @@
 #define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET		0x0708
 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET	0x070C
 #define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET		0x0710
+
 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET	0x0714
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SCL_ALT1	0x00
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SDA_ALT1	BIT(0)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_RX_DATA_ALT2	BIT(1)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_TX_BCLK_ALT2	(BIT(1) | BIT(0))
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO06_ALT3	BIT(2)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO07_ALT3	(BIT(2) | BIT(1))
+
 #define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET		0x0718
 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET	0x071C
 #define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET		0x0720

plat/imx/imx7/common/imx7.mk

+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Architecture
+$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
+
+TF_CFLAGS	+=	-mfpu=neon
+ASFLAGS		+=	-mfpu=neon
+
+# Platform
+PLAT_INCLUDES		:=	-Idrivers/imx/uart			\
+				-Iplat/imx/common/include		\
+				-Iplat/imx/imx7/include			\
+				-Idrivers/imx/timer			\
+				-Idrivers/imx/usdhc			\
+
+# Translation tables library
+include lib/xlat_tables_v2/xlat_tables.mk
+
+BL2_SOURCES		+=	common/desc_image_load.c			\
+				drivers/delay_timer/delay_timer.c		\
+				drivers/mmc/mmc.c				\
+				drivers/io/io_block.c				\
+				drivers/io/io_fip.c				\
+				drivers/io/io_memmap.c				\
+				drivers/io/io_storage.c				\
+				drivers/imx/timer/imx_gpt.c			\
+				drivers/imx/uart/imx_uart.c			\
+				drivers/imx/uart/imx_crash_uart.S		\
+				lib/aarch32/arm32_aeabi_divmod.c		\
+				lib/aarch32/arm32_aeabi_divmod_a32.S		\
+				lib/cpus/aarch32/cortex_a7.S			\
+				lib/optee/optee_utils.c				\
+				plat/imx/common/imx_aips.c			\
+				plat/imx/common/imx_caam.c			\
+				plat/imx/common/imx_clock.c			\
+				plat/imx/common/imx_csu.c			\
+				plat/imx/common/imx_io_mux.c			\
+				plat/imx/common/imx_snvs.c			\
+				plat/imx/common/imx_wdog.c			\
+				plat/imx/common/imx7_clock.c			\
+				plat/imx/imx7/common/imx7_bl2_mem_params_desc.c	\
+				plat/imx/imx7/common/imx7_bl2_el3_common.c	\
+				plat/imx/imx7/common/imx7_helpers.S		\
+				plat/imx/imx7/common/imx7_image_load.c		\
+				plat/imx/imx7/common/imx7_io_storage.c		\
+				plat/imx/common/aarch32/imx_uart_console.S	\
+				${XLAT_TABLES_LIB_SRCS}
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+
+include drivers/auth/mbedtls/mbedtls_crypto.mk
+include drivers/auth/mbedtls/mbedtls_x509.mk
+
+AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
+			drivers/auth/crypto_mod.c		\
+			drivers/auth/img_parser_mod.c		\
+			drivers/auth/tbbr/tbbr_cot.c
+
+BL2_SOURCES		+=	${AUTH_SOURCES}					\
+				plat/common/tbbr/plat_tbbr.c			\
+				plat/imx/imx7/common/imx7_trusted_boot.c	\
+				plat/imx/imx7/common/imx7_rotpk.S
+
+ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
+ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
+
+$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
+$(eval $(call MAKE_LIB_DIRS))
+
+$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH)
+
+certificates: $(ROT_KEY)
+
+$(ROT_KEY): | $(BUILD_PLAT)
+	@echo "  OPENSSL $@"
+	@if [ ! -f $(ROT_KEY) ]; then \
+		openssl genrsa 2048 > $@ 2>/dev/null; \
+	fi
+
+$(ROTPK_HASH): $(ROT_KEY)
+	@echo "  OPENSSL $@"
+	$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+	openssl dgst -sha256 -binary > $@ 2>/dev/null
+endif
+
+# Add the build options to pack BLx images and kernel device tree
+# in the FIP if the platform requires.
+ifneq ($(BL2),)
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
+endif
+ifneq ($(HW_CONFIG),)
+$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
+endif
+
+# Verify build config
+# -------------------
+
+ifeq (${ARCH},aarch64)
+  $(error Error: AArch64 not supported on i.mx7)
+endif

plat/imx/imx7/common/imx7_bl2_el3_common.c

+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <drivers/mmc.h>
+#include <lib/xlat_tables/xlat_mmu_helpers.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <lib/mmio.h>
+#include <lib/optee_utils.h>
+#include <lib/utils.h>
+
+#include <imx_aips.h>
+#include <imx_caam.h>
+#include <imx_clock.h>
+#include <imx_csu.h>
+#include <imx_gpt.h>
+#include <imx_uart.h>
+#include <imx_snvs.h>
+#include <imx_wdog.h>
+#include <imx7_def.h>
+
+#ifndef AARCH32_SP_OPTEE
+#error "Must build with OPTEE support included"
+#endif
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+	return IMX7_UBOOT_BASE;
+}
+
+static uint32_t imx7_get_spsr_for_bl32_entry(void)
+{
+	return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
+			   DISABLE_ALL_EXCEPTIONS);
+}
+
+static uint32_t imx7_get_spsr_for_bl33_entry(void)
+{
+	return SPSR_MODE32(MODE32_svc,
+			   plat_get_ns_image_entrypoint() & 0x1,
+			   SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+	int err = 0;
+	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+	bl_mem_params_node_t *hw_cfg_mem_params = NULL;
+
+	bl_mem_params_node_t *pager_mem_params = NULL;
+	bl_mem_params_node_t *paged_mem_params = NULL;
+
+	assert(bl_mem_params);
+
+	switch (image_id) {
+	case BL32_IMAGE_ID:
+		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+		assert(pager_mem_params);
+
+		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+		assert(paged_mem_params);
+
+		err = parse_optee_header(&bl_mem_params->ep_info,
+					 &pager_mem_params->image_info,
+					 &paged_mem_params->image_info);
+		if (err != 0)
+			WARN("OPTEE header parse error.\n");
+
+		/*
+		 * When ATF loads the DTB the address of the DTB is passed in
+		 * arg2, if an hw config image is present use the base address
+		 * as DTB address an pass it as arg2
+		 */
+		hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
+
+		bl_mem_params->ep_info.args.arg0 =
+					bl_mem_params->ep_info.args.arg1;
+		bl_mem_params->ep_info.args.arg1 = 0;
+		if (hw_cfg_mem_params)
+			bl_mem_params->ep_info.args.arg2 =
+					hw_cfg_mem_params->image_info.image_base;
+		else
+			bl_mem_params->ep_info.args.arg2 = 0;
+		bl_mem_params->ep_info.args.arg3 = 0;
+		bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl32_entry();
+		break;
+
+	case BL33_IMAGE_ID:
+		/* AArch32 only core: OP-TEE expects NSec EP in register LR */
+		pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
+		assert(pager_mem_params);
+		pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
+
+		/* BL33 expects to receive the primary CPU MPID (through r0) */
+		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+		bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl33_entry();
+		break;
+
+	default:
+		/* Do nothing in default case */
+		break;
+	}
+
+	return err;
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+	/* Setup the MMU here */
+}
+
+static void imx7_setup_system_counter(void)
+{
+	unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
+
+	/* Set the frequency table index to our target frequency */
+	write_cntfrq(freq);
+
+	/* Enable system counter @ frequency table index 0, halt on debug */
+	mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
+		      CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
+}
+
+static void imx7_setup_wdog_clocks(void)
+{
+	uint32_t wdog_en_bits = (uint32_t)WDOG_DEFAULT_CLK_SELECT;
+
+	imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
+	imx_clock_enable_wdog(0);
+	imx_clock_enable_wdog(1);
+	imx_clock_enable_wdog(2);
+	imx_clock_enable_wdog(3);
+}
+
+
+/*
+ * bl2_el3_early_platform_setup()
+ * MMU off
+ */
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+				  u_register_t arg3, u_register_t arg4)
+{
+	static console_imx_uart_t console;
+	int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
+
+	/* Initialize common components */
+	imx_aips_init();
+	imx_csu_init();
+	imx_snvs_init();
+	imx_gpt_ops_init(GPT1_BASE_ADDR);
+	imx_clock_init();
+	imx7_setup_system_counter();
+	imx7_setup_wdog_clocks();
+
+	/* Platform specific setup */
+	imx7_platform_setup(arg1, arg2, arg3, arg4);
+
+	/* Init UART, clock should be enabled in imx7_platform_setup() */
+	console_imx_uart_register(PLAT_IMX7_BOOT_UART_BASE,
+				  PLAT_IMX7_BOOT_UART_CLK_IN_HZ,
+				  PLAT_IMX7_CONSOLE_BAUDRATE,
+				  &console);
+	console_set_scope(&console.console, console_scope);
+
+	/* Open handles to persistent storage */
+	plat_imx7_io_setup();
+
+	/* Setup higher-level functionality CAAM, RTC etc */
+	imx_caam_init();
+	imx_wdog_init();
+
+	/* Print out the expected memory map */
+	VERBOSE("\tOPTEE       0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT);
+	VERBOSE("\tATF/BL2     0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
+	VERBOSE("\tSHRAM       0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
+	VERBOSE("\tFIP         0x%08x-0x%08x\n", IMX7_FIP_BASE, IMX7_FIP_LIMIT);
+	VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT);
+	VERBOSE("\tDTB         0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT);
+	VERBOSE("\tUBOOT/BL33  0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT);
+}
+
+/*
+ * bl2_platform_setup()
+ * MMU on - enabled by bl2_el3_plat_arch_setup()
+ */
+void bl2_platform_setup(void)
+{
+}

plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c → plat/imx/imx7/common/imx7_bl2_mem_params_desc.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,8 +22,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
 				      image_info_t, 0),
 
-		.image_info.image_base = WARP7_OPTEE_BASE,
-		.image_info.image_max_size = WARP7_OPTEE_SIZE,
+		.image_info.image_base = IMX7_OPTEE_BASE,
+		.image_info.image_max_size = IMX7_OPTEE_SIZE,
 
 		.next_handoff_image_id = BL33_IMAGE_ID,
 	},
@@ -36,8 +36,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
 
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
 				      image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-		.image_info.image_base = WARP7_OPTEE_BASE,
-		.image_info.image_max_size = WARP7_OPTEE_SIZE,
+		.image_info.image_base = IMX7_OPTEE_BASE,
+		.image_info.image_max_size = IMX7_OPTEE_SIZE,
 
 		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
@@ -70,8 +70,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
 
 			SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 					      VERSION_2, image_info_t, 0),
-			.image_info.image_base = WARP7_UBOOT_BASE,
-			.image_info.image_max_size = WARP7_UBOOT_SIZE,
+			.image_info.image_base = IMX7_UBOOT_BASE,
+			.image_info.image_max_size = IMX7_UBOOT_SIZE,
 		# endif /* PRELOADED_BL33_BASE */
 
 		.next_handoff_image_id = INVALID_IMAGE_ID,

plat/imx/imx7/warp7/aarch32/warp7_helpers.S → plat/imx/imx7/common/imx7_helpers.S

 /*
- * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ * Copyright (c) Linaro 2018-2019 Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,14 +35,14 @@ func plat_get_my_entrypoint
 endfunc plat_get_my_entrypoint
 
 func plat_crash_console_init
-	mov_imm	r0, PLAT_WARP7_BOOT_UART_BASE
-	mov_imm	r1, PLAT_WARP7_BOOT_UART_CLK_IN_HZ
-	mov_imm	r2, PLAT_WARP7_CONSOLE_BAUDRATE
+	mov_imm	r0, PLAT_IMX7_BOOT_UART_BASE
+	mov_imm	r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ
+	mov_imm	r2, PLAT_IMX7_CONSOLE_BAUDRATE
 	b	imx_crash_uart_init
 endfunc plat_crash_console_init
 
 func plat_crash_console_putc
-	mov_imm r1, PLAT_WARP7_BOOT_UART_BASE
+	mov_imm r1, PLAT_IMX7_BOOT_UART_BASE
 	b	imx_crash_uart_putc
 endfunc plat_crash_console_putc
 

plat/imx/imx7/warp7/warp7_io_storage.c → plat/imx/imx7/common/imx7_io_storage.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,21 +19,21 @@
 static const io_dev_connector_t *fip_dev_con;
 static uintptr_t fip_dev_handle;
 
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
 static const io_dev_connector_t *mmc_dev_con;
 static uintptr_t mmc_dev_handle;
 
 static const io_block_spec_t mmc_fip_spec = {
-	.offset = WARP7_FIP_MMC_BASE,
-	.length = WARP7_FIP_SIZE
+	.offset = IMX7_FIP_MMC_BASE,
+	.length = IMX7_FIP_SIZE
 };
 
 static const io_block_dev_spec_t mmc_dev_spec = {
 	/* It's used as temp buffer in block driver. */
 	.buffer		= {
-		.offset	= WARP7_FIP_BASE,
+		.offset	= IMX7_FIP_BASE,
 		/* do we need a new value? */
-		.length = WARP7_FIP_SIZE
+		.length = IMX7_FIP_SIZE
 	},
 	.ops		= {
 		.read	= mmc_read_blocks,
@@ -49,8 +49,8 @@ static const io_dev_connector_t *memmap_dev_con;
 static uintptr_t memmap_dev_handle;
 
 static const io_block_spec_t fip_block_spec = {
-	.offset = WARP7_FIP_BASE,
-	.length = WARP7_FIP_SIZE
+	.offset = IMX7_FIP_BASE,
+	.length = IMX7_FIP_SIZE
 };
 static int open_memmap(const uintptr_t spec);
 #endif
@@ -106,7 +106,7 @@ struct plat_io_policy {
 };
 
 static const struct plat_io_policy policies[] = {
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
 	[FIP_IMAGE_ID] = {
 		&mmc_dev_handle,
 		(uintptr_t)&mmc_fip_spec,
@@ -190,7 +190,7 @@ static int open_fip(const uintptr_t spec)
 	return result;
 }
 
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
 static int open_mmc(const uintptr_t spec)
 {
 	int result;
@@ -240,11 +240,11 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
 	return result;
 }
 
-void plat_warp7_io_setup(void)
+void plat_imx7_io_setup(void)
 {
 	int result __unused;
 
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
 	result = register_io_dev_block(&mmc_dev_con);
 	assert(result == 0);
 

plat/imx/imx7/warp7/warp7_rotpk.S → plat/imx/imx7/common/imx7_rotpk.S

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-	.global warp7_rotpk_hash
-	.global warp7_rotpk_hash_end
-warp7_rotpk_hash:
+	.global imx7_rotpk_hash
+	.global imx7_rotpk_hash_end
+imx7_rotpk_hash:
 	/* DER header */
 	.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
 	.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
 	/* SHA256 */
 	.incbin ROTPK_HASH
-warp7_rotpk_hash_end:
+imx7_rotpk_hash_end:

plat/imx/imx7/warp7/warp7_trusted_boot.c → plat/imx/imx7/common/imx7_trusted_boot.c

@@ -6,13 +6,13 @@
 
 #include <plat/common/platform.h>
 
-extern char warp7_rotpk_hash[], warp7_rotpk_hash_end[];
+extern char imx7_rotpk_hash[], imx7_rotpk_hash_end[];
 
 int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
 			unsigned int *flags)
 {
-	*key_ptr = warp7_rotpk_hash;
-	*key_len = warp7_rotpk_hash_end - warp7_rotpk_hash;
+	*key_ptr = imx7_rotpk_hash;
+	*key_len = imx7_rotpk_hash_end - imx7_rotpk_hash;
 	*flags = ROTPK_IS_HASH;
 
 	return 0;

plat/imx/imx7/warp7/warp7_private.h → plat/imx/imx7/include/imx7_def.h

 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef WARP7_PRIVATE_H
-#define WARP7_PRIVATE_H
+#ifndef IMX7_DEF_H
+#define IMX7_DEF_H
+
+#include <stdint.h>
+
 
 /*******************************************************************************
  * Function and variable prototypes
  ******************************************************************************/
-void plat_warp7_io_setup(void);
+void plat_imx7_io_setup(void);
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+			 u_register_t arg3, u_register_t arg4);
 
-#endif /* WARP7_PRIVATE_H */
+#endif /*IMX7_DEF_H */

plat/imx/imx7/picopi/include/platform_def.h

+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <plat/common/common_def.h>
+
+#define PLATFORM_STACK_SIZE		0x1000
+
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	2
+#define PLATFORM_CLUSTER_COUNT		1
+#define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
+
+#define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
+
+#define PICOPI_PRIMARY_CPU		0
+
+#define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
+					PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
+
+#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_OFF_STATE		2
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN		0
+
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET		1
+
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF		2
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH		4
+#define PLAT_LOCAL_PSTATE_MASK		((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ * i.MX7 has a 32 byte cacheline size
+ * i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 pg 298
+ */
+#define CACHE_WRITEBACK_SHIFT		4
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+/*
+ * Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
+ */
+#define BOOT_ROM_BASE			0x00000000
+#define BOOT_ROM_SIZE			0x00020000
+
+#define OCRAM_S_BASE			0x00180000
+#define OCRAM_S_SIZE			0x00008000
+
+/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
+#define DRAM_BASE			0x80000000
+#define DRAM_SIZE			0x20000000
+#define DRAM_LIMIT			(DRAM_BASE + DRAM_SIZE)
+
+/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
+#define IMX7_OPTEE_SIZE			0x02000000
+#define IMX7_OPTEE_BASE			(DRAM_LIMIT - IMX7_OPTEE_SIZE)
+#define IMX7_OPTEE_LIMIT		(IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
+
+/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
+#define BL2_RAM_SIZE			0x00100000
+#define BL2_RAM_BASE			(IMX7_OPTEE_BASE - BL2_RAM_SIZE)
+#define BL2_RAM_LIMIT			(BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
+#define SHARED_RAM_SIZE			0x00001000
+#define SHARED_RAM_BASE			(BL2_RAM_BASE - SHARED_RAM_SIZE)
+#define SHARED_RAM_LIMIT		(SHARED_RAM_BASE + SHARED_RAM_SIZE)
+
+/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
+#define IMX7_UBOOT_SIZE			0x00100000
+#define IMX7_UBOOT_BASE			(DRAM_BASE + 0x7800000)
+#define IMX7_UBOOT_LIMIT		(IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
+
+/* Define FIP image absolute location 0x80000000 - 0x80100000 */
+#define IMX7_FIP_SIZE			0x00100000
+#define IMX7_FIP_BASE			(DRAM_BASE)
+#define IMX7_FIP_LIMIT			(IMX7_FIP_BASE + IMX7_FIP_SIZE)
+
+/* Define FIP image location at 1MB offset */
+#define IMX7_FIP_MMC_BASE		(1024 * 1024)
+
+/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
+#define IMX7_DTB_SIZE			0x00100000
+#define IMX7_DTB_BASE			(DRAM_BASE + 0x03000000)
+#define IMX7_DTB_LIMIT			(IMX7_DTB_BASE + IMX7_DTB_SIZE)
+
+/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
+#define IMX7_DTB_OVERLAY_SIZE		0x00001000
+#define IMX7_DTB_OVERLAY_BASE		IMX7_DTB_LIMIT
+#define IMX7_DTB_OVERLAY_LIMIT		(IMX7_DTB_OVERLAY_BASE + \
+					 IMX7_DTB_OVERLAY_SIZE)
+/*
+ * BL2 specific defines.
+ *
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
+#define BL2_BASE		BL2_RAM_BASE
+#define BL2_LIMIT		(BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/*
+ * BL3-2/OPTEE
+ */
+# define BL32_BASE		IMX7_OPTEE_BASE
+# define BL32_LIMIT		(IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
+
+/*
+ * BL3-3/U-BOOT
+ */
+#define BL33_BASE		IMX7_UBOOT_BASE
+#define BL33_LIMIT		(IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
+
+/*
+ * ATF's view of memory
+ *
+ * 0xa0000000 +-----------------+
+ *            |       DDR       | BL32/OPTEE
+ * 0x9e000000 +-----------------+
+ *            |       DDR       | BL23 ATF
+ * 0x9df00000 +-----------------+
+ *            |       DDR       | Shared MBOX RAM
+ * 0x9de00000 +-----------------+
+ *            |       DDR       | Unallocated
+ * 0x87900000 +-----------------+
+ *            |       DDR       | BL33/U-BOOT
+ * 0x87800000 +-----------------+
+ *            |       DDR       | Unallocated
+ * 0x83100000 +-----------------+
+ *            |       DDR       | DTB
+ * 0x83000000 +-----------------+
+ *            |       DDR       | Unallocated
+ * 0x80100000 +-----------------+
+ *            |       DDR       | FIP
+ * 0x80000000 +-----------------+
+ *            |     SOC I/0     |
+ * 0x00a00000 +-----------------+
+ *            |      OCRAM      | Not used
+ * 0x00900000 +-----------------+
+ *            |     SOC I/0     |
+ * 0x00188000 +-----------------+
+ *            |     OCRAM_S     | Not used
+ * 0x00180000 +-----------------+
+ *            |     SOC I/0     |
+ * 0x00020000 +-----------------+
+ *            |     BootROM     | BL1
+ * 0x00000000 +-----------------+
+ */
+
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#define MAX_MMAP_REGIONS		10
+#define MAX_XLAT_TABLES			6
+#define MAX_IO_DEVICES			2
+#define MAX_IO_HANDLES			3
+#define MAX_IO_BLOCK_DEVICES		1
+
+/* UART defines */
+#define PLAT_IMX7_BOOT_UART_BASE	MXC_UART5_BASE
+#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ	24000000
+#define PLAT_IMX7_CONSOLE_BAUDRATE	115200
+
+/* MMC defines */
+#ifndef PLAT_PICOPI_SD
+#define PLAT_PICOPI_SD 3
+#endif
+
+#if PLAT_PICOPI_SD == 1
+#define PLAT_PICOPI_BOOT_MMC_BASE	USDHC1_BASE
+#endif /* PLAT_PICOPI_SD == 1 */
+
+#if PLAT_PICOPI_SD == 2
+#define PLAT_PICOPI_BOOT_MMC_BASE	USDHC2_BASE
+#endif /* PLAT_PICOPI_SD == 2 */
+
+#if PLAT_PICOPI_SD == 3
+#define PLAT_PICOPI_BOOT_MMC_BASE	USDHC3_BASE
+#endif /* PLAT_PICOPI_SD == 3 */
+
+/*
+ * System counter
+ */
+#define SYS_COUNTER_FREQ_IN_TICKS	8000000		/* 8 MHz */
+
+#endif /* PLATFORM_DEF_H */

plat/imx/imx7/picopi/picopi_bl2_el3_setup.c

+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <drivers/mmc.h>
+#include <lib/utils.h>
+
+#include <imx_caam.h>
+#include <imx_clock.h>
+#include <imx_io_mux.h>
+#include <imx_uart.h>
+#include <imx_usdhc.h>
+#include <imx7_def.h>
+
+#define UART5_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+			  CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M)
+
+#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+			  CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
+			  CCM_TARGET_POST_PODF(2))
+
+#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+			CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
+
+#define PICOPI_UART5_RX_MUX \
+	IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA
+
+#define PICOPI_UART5_TX_MUX \
+	IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA
+
+#define PICOPI_SD3_FEATURES \
+	(IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K            | \
+	 IOMUXC_SW_PAD_CTL_PAD_SD3_PE                | \
+	 IOMUXC_SW_PAD_CTL_PAD_SD3_HYS               | \
+	 IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW         | \
+	 IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
+
+static void picopi_setup_pinmux(void)
+{
+	/* Configure UART5 TX */
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET,
+					 PICOPI_UART5_TX_MUX);
+	/* Configure UART5 RX */
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET,
+					 PICOPI_UART5_RX_MUX);
+
+	/* Configure USDHC3 */
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET,
+					 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B);
+
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET,
+				     PICOPI_SD3_FEATURES);
+}
+
+static void picopi_usdhc_setup(void)
+{
+	imx_usdhc_params_t params;
+	struct mmc_device_info info;
+
+	zeromem(&params, sizeof(imx_usdhc_params_t));
+	params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
+	params.clk_rate = 25000000;
+	params.bus_width = MMC_BUS_WIDTH_8;
+	info.mmc_dev_type = MMC_IS_EMMC;
+	imx_usdhc_init(&params, &info);
+}
+
+static void picopi_setup_usb_clocks(void)
+{
+	uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
+
+	imx_clock_set_usb_clk_root_bits(usb_en_bits);
+	imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
+	imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
+	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
+	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
+}
+
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+			 u_register_t arg3, u_register_t arg4)
+{
+	uint32_t uart5_en_bits = (uint32_t)UART5_CLK_SELECT;
+	uint32_t usdhc_clock_sel = PLAT_PICOPI_SD - 1;
+
+	/* Initialize clocks etc */
+	imx_clock_enable_uart(4, uart5_en_bits);
+	imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
+
+	picopi_setup_usb_clocks();
+
+	/* Setup pin-muxes */
+	picopi_setup_pinmux();
+
+	picopi_usdhc_setup();
+}

plat/imx/imx7/picopi/platform.mk

+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Include imx7 common
+include plat/imx/imx7/common/imx7.mk
+
+# Platform
+PLAT_INCLUDES		+=	-Iplat/imx/imx7/picopi/include		    \
+
+BL2_SOURCES		+=	drivers/imx/usdhc/imx_usdhc.c		    \
+				plat/imx/imx7/picopi/picopi_bl2_el3_setup.c \
+
+# Build config flags
+# ------------------
+
+ARM_CORTEX_A7			:= yes
+WORKAROUND_CVE_2017_5715	:= 0
+
+RESET_TO_BL31			:= 0
+
+# Non-TF Boot ROM
+BL2_AT_EL3			:= 1
+
+# Indicate single-core
+COLD_BOOT_SINGLE_CPU		:= 1
+
+# Have different sections for code and rodata
+SEPARATE_CODE_AND_RODATA	:= 1
+
+# Use Coherent memory
+USE_COHERENT_MEM		:= 1
+
+# Use multi console API
+MULTI_CONSOLE_API		:= 1
+
+PLAT_PICOPI_UART		:=5
+$(eval $(call add_define,PLAT_PICOPI_UART))

plat/imx/imx7/warp7/include/platform_def.h

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -74,13 +74,13 @@
 #define DRAM_LIMIT			(DRAM_BASE + DRAM_SIZE)
 
 /* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
-#define WARP7_OPTEE_SIZE		0x02000000
-#define WARP7_OPTEE_BASE		(DRAM_LIMIT - WARP7_OPTEE_SIZE)
-#define WARP7_OPTEE_LIMIT		(WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
+#define IMX7_OPTEE_SIZE			0x02000000
+#define IMX7_OPTEE_BASE			(DRAM_LIMIT - IMX7_OPTEE_SIZE)
+#define IMX7_OPTEE_LIMIT		(IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
 
 /* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
 #define BL2_RAM_SIZE			0x00100000
-#define BL2_RAM_BASE			(WARP7_OPTEE_BASE - BL2_RAM_SIZE)
+#define BL2_RAM_BASE			(IMX7_OPTEE_BASE - BL2_RAM_SIZE)
 #define BL2_RAM_LIMIT			(BL2_RAM_BASE + BL2_RAM_SIZE)
 
 /* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
@@ -89,28 +89,28 @@
 #define SHARED_RAM_LIMIT		(SHARED_RAM_BASE + SHARED_RAM_SIZE)
 
 /* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
-#define WARP7_UBOOT_SIZE		0x00100000
-#define WARP7_UBOOT_BASE		(DRAM_BASE + 0x7800000)
-#define WARP7_UBOOT_LIMIT		(WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
+#define IMX7_UBOOT_SIZE			0x00100000
+#define IMX7_UBOOT_BASE			(DRAM_BASE + 0x7800000)
+#define IMX7_UBOOT_LIMIT		(IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
 
 /* Define FIP image absolute location 0x80000000 - 0x80100000 */
-#define WARP7_FIP_SIZE			0x00100000
-#define WARP7_FIP_BASE			(DRAM_BASE)
-#define WARP7_FIP_LIMIT			(WARP7_FIP_BASE + WARP7_FIP_SIZE)
+#define IMX7_FIP_SIZE			0x00100000
+#define IMX7_FIP_BASE			(DRAM_BASE)
+#define IMX7_FIP_LIMIT			(IMX7_FIP_BASE + IMX7_FIP_SIZE)
 
 /* Define FIP image location at 1MB offset */
-#define WARP7_FIP_MMC_BASE		(1024 * 1024)
+#define IMX7_FIP_MMC_BASE		(1024 * 1024)
 
 /* Define the absolute location of DTB 0x83000000 - 0x83100000 */
-#define WARP7_DTB_SIZE			0x00100000
-#define WARP7_DTB_BASE			(DRAM_BASE + 0x03000000)
-#define WARP7_DTB_LIMIT			(WARP7_DTB_BASE + WARP7_DTB_SIZE)
+#define IMX7_DTB_SIZE			0x00100000
+#define IMX7_DTB_BASE			(DRAM_BASE + 0x03000000)
+#define IMX7_DTB_LIMIT			(IMX7_DTB_BASE + IMX7_DTB_SIZE)
 
 /* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
-#define WARP7_DTB_OVERLAY_SIZE		0x00001000
-#define WARP7_DTB_OVERLAY_BASE		WARP7_DTB_LIMIT
-#define WARP7_DTB_OVERLAY_LIMIT		(WARP7_DTB_OVERLAY_BASE + \
-					 WARP7_DTB_OVERLAY_SIZE)
+#define IMX7_DTB_OVERLAY_SIZE		0x00001000
+#define IMX7_DTB_OVERLAY_BASE		IMX7_DTB_LIMIT
+#define IMX7_DTB_OVERLAY_LIMIT		(IMX7_DTB_OVERLAY_BASE + \
+					 IMX7_DTB_OVERLAY_SIZE)
 
 /*
  * BL2 specific defines.
@@ -124,14 +124,14 @@
 /*
  * BL3-2/OPTEE
  */
-# define BL32_BASE		WARP7_OPTEE_BASE
-# define BL32_LIMIT		(WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
+# define BL32_BASE		IMX7_OPTEE_BASE
+# define BL32_LIMIT		(IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
 
 /*
  * BL3-3/U-BOOT
  */
-#define BL33_BASE		WARP7_UBOOT_BASE
-#define BL33_LIMIT		(WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
+#define BL33_BASE		IMX7_UBOOT_BASE
+#define BL33_LIMIT		(IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
 
 /*
  * ATF's view of memory
@@ -189,9 +189,9 @@
 #error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6"
 #endif
 
-#define PLAT_WARP7_BOOT_UART_BASE	PLAT_WARP7_UART_BASE
-#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ	24000000
-#define PLAT_WARP7_CONSOLE_BAUDRATE	115200
+#define PLAT_IMX7_BOOT_UART_BASE	PLAT_WARP7_UART_BASE
+#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ	24000000
+#define PLAT_IMX7_CONSOLE_BAUDRATE	115200
 
 /* MMC defines */
 #ifndef PLAT_WARP7_SD
@@ -210,13 +210,6 @@
 #define PLAT_WARP7_BOOT_MMC_BASE	USDHC3_BASE
 #endif /* PLAT_WARP7_SD == 3 */
 
-/*
- * GIC related constants
- */
-#define GICD_BASE			0x31001000
-#define GICC_BASE			0x31002000
-#define GICR_BASE			0
-
 /*
  * System counter
  */

plat/imx/imx7/warp7/platform.mk

@@ -4,106 +4,21 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-# Architecture
-$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
-
-# Tune compiler for Cortex-A7
-ifeq ($(notdir $(CC)),armclang)
-    TF_CFLAGS	+=	-mfpu=neon
-    ASFLAGS	+=	-mfpu=neon
-else ifneq ($(findstring clang,$(notdir $(CC))),)
-    TF_CFLAGS	+=	-mfpu=neon
-    ASFLAGS	+=	-mfpu=neon
-else
-    TF_CFLAGS	+=	-mfpu=neon
-    ASFLAGS	+=	-mfpu=neon
-endif
+# Include imx7 common
+include plat/imx/imx7/common/imx7.mk
 
 # Platform
-PLAT_INCLUDES		:=	-Idrivers/imx/uart			\
-				-Iplat/imx/common/include/		\
-				-Iplat/imx/imx7/warp7/include		\
-				-Idrivers/imx/timer			\
-				-Idrivers/imx/usdhc			\
-				-Iplat/imx/imx7/include
-
-# Translation tables library
-include lib/xlat_tables_v2/xlat_tables.mk
-
-BL2_SOURCES		+=	common/desc_image_load.c			\
-				drivers/delay_timer/delay_timer.c		\
-				drivers/mmc/mmc.c				\
-				drivers/io/io_block.c				\
-				drivers/io/io_fip.c				\
-				drivers/io/io_memmap.c				\
-				drivers/io/io_storage.c				\
-				drivers/imx/timer/imx_gpt.c			\
-				drivers/imx/uart/imx_uart.c			\
-				drivers/imx/uart/imx_crash_uart.S		\
-				drivers/imx/usdhc/imx_usdhc.c			\
-				lib/aarch32/arm32_aeabi_divmod.c		\
-				lib/aarch32/arm32_aeabi_divmod_a32.S		\
-				lib/cpus/aarch32/cortex_a7.S			\
-				lib/optee/optee_utils.c				\
-				plat/imx/common/imx_aips.c			\
-				plat/imx/common/imx_caam.c			\
-				plat/imx/common/imx_clock.c			\
-				plat/imx/common/imx_csu.c			\
-				plat/imx/common/imx_io_mux.c			\
-				plat/imx/common/imx_snvs.c			\
-				plat/imx/common/imx_wdog.c			\
-				plat/imx/common/imx7_clock.c		\
-				plat/imx/imx7/warp7/aarch32/warp7_helpers.S	\
-				plat/imx/imx7/warp7/warp7_bl2_el3_setup.c	\
-				plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \
-				plat/imx/imx7/warp7/warp7_io_storage.c		\
-				plat/imx/imx7/warp7/warp7_image_load.c		\
-				plat/imx/common/aarch32/imx_uart_console.S	\
-				${XLAT_TABLES_LIB_SRCS}
-
-ifneq (${TRUSTED_BOARD_BOOT},0)
-
-include drivers/auth/mbedtls/mbedtls_crypto.mk
-include drivers/auth/mbedtls/mbedtls_x509.mk
-
-AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
-			drivers/auth/crypto_mod.c		\
-			drivers/auth/img_parser_mod.c		\
-			drivers/auth/tbbr/tbbr_cot.c
-
-BL2_SOURCES		+=	${AUTH_SOURCES}					\
-				plat/common/tbbr/plat_tbbr.c			\
-				plat/imx/imx7/warp7/warp7_trusted_boot.c	\
-				plat/imx/imx7/warp7/warp7_rotpk.S
-
-ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
-ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
+PLAT_INCLUDES		+= -Iplat/imx/imx7/warp7/include
 
-$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
-$(eval $(call MAKE_LIB_DIRS))
-
-$(BUILD_PLAT)/bl2/warp7_rotpk.o: $(ROTPK_HASH)
-
-certificates: $(ROT_KEY)
-
-$(ROT_KEY): | $(BUILD_PLAT)
-	@echo "  OPENSSL $@"
-	@if [ ! -f $(ROT_KEY) ]; then \
-		openssl genrsa 2048 > $@ 2>/dev/null; \
-	fi
-
-$(ROTPK_HASH): $(ROT_KEY)
-	@echo "  OPENSSL $@"
-	$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
-	openssl dgst -sha256 -binary > $@ 2>/dev/null
-endif
+BL2_SOURCES		+=	drivers/imx/usdhc/imx_usdhc.c			\
+				plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
 
 # Build config flags
 # ------------------
 
+ARM_CORTEX_A7			:= yes
 WORKAROUND_CVE_2017_5715	:= 0
 
-# Enable reset to BL31 by default
 RESET_TO_BL31			:= 0
 
 # Non-TF Boot ROM
@@ -118,28 +33,5 @@ SEPARATE_CODE_AND_RODATA	:= 1
 # Use Coherent memory
 USE_COHERENT_MEM		:= 1
 
-# PLAT_WARP7_UART
 PLAT_WARP7_UART			:=1
 $(eval $(call add_define,PLAT_WARP7_UART))
-
-# Add the build options to pack BLx images and kernel device tree
-# in the FIP if the platform requires.
-ifneq ($(BL2),)
-$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
-endif
-ifneq ($(BL32_EXTRA1),)
-$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
-endif
-ifneq ($(BL32_EXTRA2),)
-$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
-endif
-ifneq ($(HW_CONFIG),)
-$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
-endif
-
-# Verify build config
-# -------------------
-
-ifeq (${ARCH},aarch64)
-  $(error Error: AArch64 not supported on i.mx7)
-endif

plat/imx/imx7/warp7/warp7_bl2_el3_setup.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,30 +8,17 @@
 
 #include <platform_def.h>
 
-#include <arch_helpers.h>
-#include <common/bl_common.h>
 #include <common/debug.h>
-#include <common/desc_image_load.h>
 #include <drivers/console.h>
 #include <drivers/mmc.h>
-#include <lib/xlat_tables/xlat_mmu_helpers.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/mmio.h>
-#include <lib/optee_utils.h>
 #include <lib/utils.h>
 
-#include <imx_aips.h>
 #include <imx_caam.h>
 #include <imx_clock.h>
-#include <imx_csu.h>
-#include <imx_gpt.h>
 #include <imx_io_mux.h>
 #include <imx_uart.h>
-#include <imx_snvs.h>
 #include <imx_usdhc.h>
-#include <imx_wdog.h>
-
-#include "warp7_private.h"
+#include <imx7_def.h>
 
 #define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
 			  CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M)
@@ -43,102 +30,9 @@
 			  CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
 			  CCM_TARGET_POST_PODF(2))
 
-#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
-			 CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
-
 #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
 			CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
 
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
-	return WARP7_UBOOT_BASE;
-}
-
-static uint32_t warp7_get_spsr_for_bl32_entry(void)
-{
-	return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
-			   DISABLE_ALL_EXCEPTIONS);
-}
-
-static uint32_t warp7_get_spsr_for_bl33_entry(void)
-{
-	return SPSR_MODE32(MODE32_svc,
-			   plat_get_ns_image_entrypoint() & 0x1,
-			   SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
-}
-
-#ifndef AARCH32_SP_OPTEE
-#error "Must build with OPTEE support included"
-#endif
-
-int bl2_plat_handle_post_image_load(unsigned int image_id)
-{
-	int err = 0;
-	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
-	bl_mem_params_node_t *hw_cfg_mem_params = NULL;
-
-	bl_mem_params_node_t *pager_mem_params = NULL;
-	bl_mem_params_node_t *paged_mem_params = NULL;
-
-	assert(bl_mem_params);
-
-	switch (image_id) {
-	case BL32_IMAGE_ID:
-		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
-		assert(pager_mem_params);
-
-		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
-		assert(paged_mem_params);
-
-		err = parse_optee_header(&bl_mem_params->ep_info,
-					 &pager_mem_params->image_info,
-					 &paged_mem_params->image_info);
-		if (err != 0)
-			WARN("OPTEE header parse error.\n");
-
-		/*
-		 * When ATF loads the DTB the address of the DTB is passed in
-		 * arg2, if an hw config image is present use the base address
-		 * as DTB address an pass it as arg2
-		 */
-		hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
-
-		bl_mem_params->ep_info.args.arg0 =
-					bl_mem_params->ep_info.args.arg1;
-		bl_mem_params->ep_info.args.arg1 = 0;
-		if (hw_cfg_mem_params)
-			bl_mem_params->ep_info.args.arg2 =
-					hw_cfg_mem_params->image_info.image_base;
-		else
-			bl_mem_params->ep_info.args.arg2 = 0;
-		bl_mem_params->ep_info.args.arg3 = 0;
-		bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry();
-		break;
-
-	case BL33_IMAGE_ID:
-		/* AArch32 only core: OP-TEE expects NSec EP in register LR */
-		pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
-		assert(pager_mem_params);
-		pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
-
-		/* BL33 expects to receive the primary CPU MPID (through r0) */
-		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
-		bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry();
-		break;
-
-	default:
-		/* Do nothing in default case */
-		break;
-	}
-
-	return err;
-}
-
-void bl2_el3_plat_arch_setup(void)
-{
-	/* Setup the MMU here */
-}
-
 #define WARP7_UART1_TX_MUX \
 	IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA
 
@@ -215,29 +109,6 @@ static void warp7_usdhc_setup(void)
 	imx_usdhc_init(&params, &info);
 }
 
-static void warp7_setup_system_counter(void)
-{
-	unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
-
-	/* Set the frequency table index to our target frequency */
-	write_cntfrq(freq);
-
-	/* Enable system counter @ frequency table index 0, halt on debug */
-	mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
-		      CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
-}
-
-static void warp7_setup_wdog_clocks(void)
-{
-	uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT;
-
-	imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
-	imx_clock_enable_wdog(0);
-	imx_clock_enable_wdog(1);
-	imx_clock_enable_wdog(2);
-	imx_clock_enable_wdog(3);
-}
-
 static void warp7_setup_usb_clocks(void)
 {
 	uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
@@ -248,67 +119,24 @@ static void warp7_setup_usb_clocks(void)
 	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
 	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
 }
-/*
- * bl2_el3_early_platform_setup()
- * MMU off
- */
-void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
 			 u_register_t arg3, u_register_t arg4)
 {
 	uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
 	uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
 	uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
-	static console_imx_uart_t console;
-	int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
-
-	/* Initialize the AIPS */
-	imx_aips_init();
-	imx_csu_init();
-	imx_snvs_init();
-	imx_gpt_ops_init(GPT1_BASE_ADDR);
 
-	/* Initialize clocks, regulators, pin-muxes etc */
-	imx_clock_init();
+	/* Initialize clocks etc */
 	imx_clock_enable_uart(0, uart1_en_bits);
 	imx_clock_enable_uart(5, uart6_en_bits);
+
 	imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
-	warp7_setup_system_counter();
-	warp7_setup_wdog_clocks();
+
 	warp7_setup_usb_clocks();
 
 	/* Setup pin-muxes */
 	warp7_setup_pinmux();
 
-	/* Init UART, storage and friends */
-	console_imx_uart_register(PLAT_WARP7_BOOT_UART_BASE,
-				  PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
-				  PLAT_WARP7_CONSOLE_BAUDRATE,
-				  &console);
-	console_set_scope(&console.console, console_scope);
-
 	warp7_usdhc_setup();
-
-	/* Open handles to persistent storage */
-	plat_warp7_io_setup();
-
-	/* Setup higher-level functionality CAAM, RTC etc */
-	imx_caam_init();
-	imx_wdog_init();
-
-	/* Print out the expected memory map */
-	VERBOSE("\tOPTEE       0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT);
-	VERBOSE("\tATF/BL2     0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
-	VERBOSE("\tSHRAM       0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
-	VERBOSE("\tFIP         0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT);
-	VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", WARP7_DTB_OVERLAY_BASE, WARP7_DTB_OVERLAY_LIMIT);
-	VERBOSE("\tDTB         0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT);
-	VERBOSE("\tUBOOT/BL33  0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT);
-}
-
-/*
- * bl2_platform_setup()
- * MMU on - enabled by bl2_el3_plat_arch_setup()
- */
-void bl2_platform_setup(void)
-{
 }