From e10842167b5529a45433ba9e33097dc853065aba Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 29 Oct 2015 10:37:28 +0530 Subject: [PATCH] Tegra: init normal/crash console for platforms The BL2 fills in the UART controller ID to be used as the normal as well as the crash console on Tegra platforms. The controller ID to UART controller base address mapping is handled by each Tegra SoC the base addresses might change across Tegra chips. This patch adds the handler to parse the platform params to get the UART ID for the per-soc handlers. Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa Signed-off-by: Varun Wadekar --- docs/plat/nvidia-tegra.md | 7 ++-- .../tegra/common/aarch64/tegra_helpers.S | 14 ++++++-- plat/nvidia/tegra/common/tegra_bl31_setup.c | 33 ++++++++++++------- plat/nvidia/tegra/include/t132/tegra_def.h | 9 +++++ plat/nvidia/tegra/include/t210/tegra_def.h | 9 +++++ plat/nvidia/tegra/include/tegra_private.h | 3 ++ plat/nvidia/tegra/soc/t132/plat_setup.c | 28 ++++++++++++++++ plat/nvidia/tegra/soc/t132/platform_t132.mk | 3 -- plat/nvidia/tegra/soc/t210/plat_setup.c | 28 ++++++++++++++++ plat/nvidia/tegra/soc/t210/platform_t210.mk | 3 -- 10 files changed, 116 insertions(+), 21 deletions(-) diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index e6ec46228..f82085b13 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -65,14 +65,17 @@ to the build command line. The Tegra platform code expects a pointer to the following platform specific structure via 'x1' register from the BL2 layer which is used by the bl31_early_platform_setup() handler to extract the TZDRAM carveout base and -size for loading the Trusted OS. The Tegra memory controller driver programs -this base/size in order to restrict NS accesses. +size for loading the Trusted OS and the UART port ID to be used. The Tegra +memory controller driver programs this base/size in order to restrict NS +accesses. typedef struct plat_params_from_bl2 { /* TZ memory size */ uint64_t tzdram_size; /* TZ memory base */ uint64_t tzdram_base; + /* UART port ID */ + int uart_id; } plat_params_from_bl2_t; Power Management diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index b2fc9a75b..6851b1502 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -66,6 +66,7 @@ .globl tegra_sec_entry_point .globl ns_image_entrypoint .globl tegra_bl31_phys_base + .globl tegra_console_base /* --------------------- * Common CPU init code @@ -226,7 +227,8 @@ endfunc platform_mem_init * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, TEGRA_BOOT_UART_BASE + adr x0, tegra_console_base + ldr x0, [x0] mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ mov_imm x2, TEGRA_CONSOLE_BAUDRATE b console_core_init @@ -240,7 +242,8 @@ endfunc plat_crash_console_init * --------------------------------------------- */ func plat_crash_console_putc - mov_imm x1, TEGRA_BOOT_UART_BASE + adr x1, tegra_console_base + ldr x1, [x1] b console_core_putc endfunc plat_crash_console_putc @@ -402,3 +405,10 @@ ns_image_entrypoint: */ tegra_bl31_phys_base: .quad 0 + + /* -------------------------------------------------- + * UART controller base for console init + * -------------------------------------------------- + */ +tegra_console_base: + .quad 0 diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index f762d6a06..3a9514bda 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -55,6 +55,7 @@ extern unsigned long __RO_END__; extern unsigned long __BL31_END__; extern uint64_t tegra_bl31_phys_base; +extern uint64_t tegra_console_base; /* * The next 3 constants identify the extents of the code, RO data region and the @@ -114,17 +115,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, #if DEBUG int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; #endif - /* - * Configure the UART port to be used as the console - */ - console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ, - TEGRA_CONSOLE_BAUDRATE); - - /* Initialise crash console */ - plat_crash_console_init(); - - INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? - "Denver" : "ARM", read_mpidr()); /* * Copy BL3-3, BL3-2 entry point information. @@ -142,6 +132,27 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, assert(plat_params); plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; + plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; + + /* + * Get the base address of the UART controller to be used for the + * console + */ + assert(plat_params->uart_id); + tegra_console_base = plat_get_console_from_id(plat_params->uart_id); + + /* + * Configure the UART port to be used as the console + */ + assert(tegra_console_base); + console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, + TEGRA_CONSOLE_BAUDRATE); + + /* Initialise crash console */ + plat_crash_console_init(); + + INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? + "Denver" : "ARM", read_mpidr()); } /******************************************************************************* diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index 683c90381..09d9b7429 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -70,6 +70,15 @@ ******************************************************************************/ #define TEGRA_EVP_BASE 0x6000F000 +/******************************************************************************* + * Tegra UART controller base addresses + ******************************************************************************/ +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTE_BASE 0x70006400 + /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index ca78d50e6..8be39bb32 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -95,6 +95,15 @@ ******************************************************************************/ #define TEGRA_EVP_BASE 0x6000F000 +/******************************************************************************* + * Tegra UART controller base addresses + ******************************************************************************/ +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTE_BASE 0x70006400 + /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index 9e6602338..75416ec3c 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -47,6 +47,8 @@ typedef struct plat_params_from_bl2 { uint64_t tzdram_size; /* TZ memory base */ uint64_t tzdram_base; + /* UART port ID */ + int uart_id; } plat_params_from_bl2_t; /* Declarations for plat_psci_handlers.c */ @@ -55,6 +57,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, /* Declarations for plat_setup.c */ const mmap_region_t *plat_get_mmio_map(void); +uint32_t plat_get_console_from_id(int id); /* Declarations for plat_secondary.c */ void plat_secondary_setup(void); diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c index 0d6641375..337a2c59f 100644 --- a/plat/nvidia/tegra/soc/t132/plat_setup.c +++ b/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -78,3 +78,31 @@ unsigned int plat_get_syscnt_freq2(void) { return 12000000; } + +/******************************************************************************* + * Maximum supported UART controllers + ******************************************************************************/ +#define TEGRA132_MAX_UART_PORTS 5 + +/******************************************************************************* + * This variable holds the UART port base addresses + ******************************************************************************/ +static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = { + 0, /* undefined - treated as an error case */ + TEGRA_UARTA_BASE, + TEGRA_UARTB_BASE, + TEGRA_UARTC_BASE, + TEGRA_UARTD_BASE, + TEGRA_UARTE_BASE, +}; + +/******************************************************************************* + * Retrieve the UART controller base to be used as the console + ******************************************************************************/ +uint32_t plat_get_console_from_id(int id) +{ + if (id > TEGRA132_MAX_UART_PORTS) + return 0; + + return tegra132_uart_addresses[id]; +} diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk index 466e7cd36..6b9fce3b4 100644 --- a/plat/nvidia/tegra/soc/t132/platform_t132.mk +++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -28,9 +28,6 @@ # POSSIBILITY OF SUCH DAMAGE. # -TEGRA_BOOT_UART_BASE := 0x70006300 -$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) - TZDRAM_BASE := 0xF5C00000 $(eval $(call add_define,TZDRAM_BASE)) diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c index 70a55c696..246faf874 100644 --- a/plat/nvidia/tegra/soc/t210/plat_setup.c +++ b/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -84,3 +84,31 @@ unsigned int plat_get_syscnt_freq2(void) { return 19200000; } + +/******************************************************************************* + * Maximum supported UART controllers + ******************************************************************************/ +#define TEGRA210_MAX_UART_PORTS 5 + +/******************************************************************************* + * This variable holds the UART port base addresses + ******************************************************************************/ +static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { + 0, /* undefined - treated as an error case */ + TEGRA_UARTA_BASE, + TEGRA_UARTB_BASE, + TEGRA_UARTC_BASE, + TEGRA_UARTD_BASE, + TEGRA_UARTE_BASE, +}; + +/******************************************************************************* + * Retrieve the UART controller base to be used as the console + ******************************************************************************/ +uint32_t plat_get_console_from_id(int id) +{ + if (id > TEGRA210_MAX_UART_PORTS) + return 0; + + return tegra210_uart_addresses[id]; +} diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index 76bc113d4..d83c54db0 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -28,9 +28,6 @@ # POSSIBILITY OF SUCH DAMAGE. # -TEGRA_BOOT_UART_BASE := 0x70006000 -$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) - TZDRAM_BASE := 0xFDC00000 $(eval $(call add_define,TZDRAM_BASE)) -- GitLab