diff --git a/Makefile b/Makefile
index 1069cd5ae0495cc5b99c1b1cef7e66198455a375..44a143d41902f620b6fac2222bfdd4db7bbd1fbf 100644
--- a/Makefile
+++ b/Makefile
@@ -160,6 +160,7 @@ INCLUDES		+=	-Iinclude/bl1			\
 				-Iinclude/drivers/arm		\
 				-Iinclude/lib			\
 				-Iinclude/lib/aarch64		\
+				-Iinclude/plat/common		\
 				-Iinclude/stdlib		\
 				-Iinclude/stdlib/sys		\
 				-Iplat/${PLAT}			\
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index 81c544359d51056ddfc0ecd82efadbe7621bb163..9ee8a72ed0d06f1e00da5c9026c838e05b79797d 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -28,7 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <platform.h>
+#include <platform_def.h>
 
 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index dff5b453d25dd5d09503552b475a0b457d3e46d2..1ce7930c6cf63e2c43c0dc1193ee96981d914f92 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -35,6 +35,7 @@
 #include <bl1.h>
 #include <debug.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <stdio.h>
 #include "bl1_private.h"
 
diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S
index edb676af21bc67a28488ad4faf5b16a2b7eb8527..c1eb718e820c5d4ec11dce8809ed8492a8ba60c0 100644
--- a/bl2/bl2.ld.S
+++ b/bl2/bl2.ld.S
@@ -28,7 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <platform.h>
+#include <platform_def.h>
 
 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index 563a154efb8afd98ff64d67da283b8a1fd848616..7d1863916555d39872f6bb7764966882ffe1dd59 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -35,6 +35,7 @@
 #include <bl2.h>
 #include <debug.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <stdio.h>
 #include "bl2_private.h"
 
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 4789b33ba3bb1ad46d3ae4921cfe2fa25de9adcc..7e119c58cbd85f3e91c5ea9217ee3a430fbb4de1 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -32,7 +32,7 @@
 #include <asm_macros.S>
 #include <context.h>
 #include <interrupt_mgmt.h>
-#include <platform.h>
+#include <platform_def.h>
 #include <runtime_svc.h>
 
 	.globl	runtime_exceptions
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 1b818f5ebf49fdee8be9a9cb58f79190d4ad1195..1040b7f20aa51e852e8d695a032dcbc6351dd2f3 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -28,7 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <platform.h>
+#include <platform_def.h>
 
 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c
index 78bfa89d1d4f44c137c084b9861ec25b89416b87..6f086f8cc2436f998be90193d199b762443df29f 100644
--- a/bl31/context_mgmt.c
+++ b/bl31/context_mgmt.c
@@ -37,6 +37,7 @@
 #include <context_mgmt.h>
 #include <interrupt_mgmt.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <runtime_svc.h>
 
 /*******************************************************************************
diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S
index 559ae3d3bc504ae208f307dc86587899ba709585..d26a585b3d0097f0599b8a0a6d567a8b0338360a 100644
--- a/bl32/tsp/tsp.ld.S
+++ b/bl32/tsp/tsp.ld.S
@@ -28,7 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <platform.h>
+#include <platform_def.h>
 
 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c
index 5719c063efa7981403657fa8e8ddcaf0cc7bdddd..d01ec438020c2084bcea62276dde328b471366a2 100644
--- a/bl32/tsp/tsp_interrupt.c
+++ b/bl32/tsp/tsp_interrupt.c
@@ -31,6 +31,7 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <debug.h>
+#include <fvp_def.h>
 #include <gic_v2.h>
 #include <tsp.h>
 #include <platform.h>
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index ad7ee0a2074d7b32ffb971428a12fffd837ce1f7..05737aef6f85dbc9ca3056104aed6d6d10ee47b3 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -33,6 +33,7 @@
 #include <bl32.h>
 #include <debug.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <spinlock.h>
 #include <stdio.h>
 #include <tsp.h>
diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c
index f66ff9fa5a073a19c4a60fb68ef856e4cf2d2795..366640f40cf7a3d24d2e30e956a7621465d42c17 100644
--- a/bl32/tsp/tsp_timer.c
+++ b/bl32/tsp/tsp_timer.c
@@ -29,6 +29,7 @@
  */
 #include <arch_helpers.h>
 #include <assert.h>
+#include <platform.h>
 #include <tsp.h>
 
 /*******************************************************************************
diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c
index 02f7f9556e1ab90a905524e0bfa68cc85ffa66d3..af10f214276901043e725cff52b00d248fed5579 100644
--- a/drivers/arm/cci400/cci400.c
+++ b/drivers/arm/cci400/cci400.c
@@ -30,7 +30,7 @@
 
 #include <cci400.h>
 #include <mmio.h>
-#include <platform.h>
+#include <platform_def.h>
 
 static inline unsigned long get_slave_iface_base(unsigned long mpidr)
 {
diff --git a/drivers/arm/pl011/pl011.c b/drivers/arm/pl011/pl011.c
index f12bd23d0c4e3cd121c7e29299a2c67bae3ad59e..e296c23fee539f2d6a5460eae64262ffe278cdd4 100644
--- a/drivers/arm/pl011/pl011.c
+++ b/drivers/arm/pl011/pl011.c
@@ -29,7 +29,6 @@
  */
 
 #include <assert.h>
-#include <platform.h>
 #include <pl011.h>
 
 void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate)
diff --git a/drivers/arm/pl011/pl011_console.c b/drivers/arm/pl011/pl011_console.c
index 06e357f9e6e72496ab19dfe5b09691310e3e73ce..0e82aa21b79faa805d265ceb5b56a1d128433761 100644
--- a/drivers/arm/pl011/pl011_console.c
+++ b/drivers/arm/pl011/pl011_console.c
@@ -30,7 +30,6 @@
 
 #include <assert.h>
 #include <console.h>
-#include <platform.h>
 #include <pl011.h>
 
 static unsigned long uart_base;
diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c
index 8ed7f473147417761eb7e538ada05cc0adc61382..36788a2485b14dd843bffe138ab2f27452423ec1 100644
--- a/drivers/io/io_fip.c
+++ b/drivers/io/io_fip.c
@@ -29,6 +29,7 @@
  */
 
 #include <assert.h>
+#include <bl_common.h>
 #include <debug.h>
 #include <errno.h>
 #include <firmware_image_package.h>
@@ -36,6 +37,7 @@
 #include <io_fip.h>
 #include <io_storage.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <stdint.h>
 #include <string.h>
 #include <uuid.h>
diff --git a/include/bl32/payloads/tsp.h b/include/bl32/payloads/tsp.h
index 237ad48304dee7a9b70c162ddda66d2b0a7018a1..2db3b3467638231948754bda3cc282801b61cc6f 100644
--- a/include/bl32/payloads/tsp.h
+++ b/include/bl32/payloads/tsp.h
@@ -113,7 +113,7 @@
 #ifndef __ASSEMBLY__
 
 #include <cassert.h>
-#include <platform.h>	/* For CACHE_WRITEBACK_GRANULE */
+#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */
 #include <spinlock.h>
 #include <stdint.h>
 
diff --git a/include/drivers/io_driver.h b/include/drivers/io_driver.h
index f34c71d554e11530caf72b525422c5efbfc5df4b..867abbfa32c06728bfa1ec90d4082701f7e3ac12 100644
--- a/include/drivers/io_driver.h
+++ b/include/drivers/io_driver.h
@@ -32,7 +32,7 @@
 #define __IO_DRIVER_H__
 
 #include <io_storage.h>
-#include <platform.h>   /* For MAX_IO_DEVICES */
+#include <platform_def.h> /* For MAX_IO_DEVICES */
 #include <stdint.h>
 
 
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index e6744a51ef52b59e68e2bff402df14a2dfd9a02c..037fa7d18443cff044a7da68873e4ca17369cab1 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -31,7 +31,7 @@
 #ifndef __BAKERY_LOCK_H__
 #define __BAKERY_LOCK_H__
 
-#include <platform.h>
+#include <platform_def.h>
 
 #define BAKERY_LOCK_MAX_CPUS		PLATFORM_CORE_COUNT
 
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
new file mode 100644
index 0000000000000000000000000000000000000000..cd2a8552553ae030c5fb1e14a5a4da1b6b01c55a
--- /dev/null
+++ b/include/plat/common/platform.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+#include <stdint.h>
+
+
+/*******************************************************************************
+ * Forward declarations
+ ******************************************************************************/
+struct plat_pm_ops;
+struct meminfo;
+struct image_info;
+struct el_change_info;
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void bl1_plat_arch_setup(void);
+void bl2_plat_arch_setup(void);
+void bl31_plat_arch_setup(void);
+int platform_setup_pm(const struct plat_pm_ops **);
+unsigned int platform_get_core_pos(unsigned long mpidr);
+void enable_mmu_el1(void);
+void enable_mmu_el3(void);
+void configure_mmu_el1(unsigned long total_base,
+		       unsigned long total_size,
+		       unsigned long,
+		       unsigned long,
+		       unsigned long,
+		       unsigned long);
+void configure_mmu_el3(unsigned long total_base,
+		       unsigned long total_size,
+		       unsigned long,
+		       unsigned long,
+		       unsigned long,
+		       unsigned long);
+void plat_report_exception(unsigned long);
+unsigned long plat_get_ns_image_entrypoint(void);
+unsigned long platform_get_stack(unsigned long mpidr);
+uint64_t plat_get_syscnt_freq(void);
+uint32_t ic_get_pending_interrupt_id(void);
+uint32_t ic_get_pending_interrupt_type(void);
+uint32_t ic_acknowledge_interrupt(void);
+uint32_t ic_get_interrupt_type(uint32_t id);
+void ic_end_of_interrupt(uint32_t id);
+uint32_t plat_interrupt_type_to_line(uint32_t type,
+				     uint32_t security_state);
+
+int plat_get_max_afflvl(void);
+unsigned int plat_get_aff_count(unsigned int, unsigned long);
+unsigned int plat_get_aff_state(unsigned int, unsigned long);
+int plat_get_image_source(const char *image_name,
+			uintptr_t *dev_handle,
+			uintptr_t *image_spec);
+
+/*
+ * Before calling this function BL2 is loaded in memory and its entrypoint
+ * is set by load_image. This is a placeholder for the platform to change
+ * the entrypoint of BL2 and set SPSR and security state.
+ * On FVP we are only setting the security state, entrypoint
+ */
+void bl1_plat_bl2_loaded(struct image_info *image,
+			 struct el_change_info *ep);
+
+/*
+ * Before calling this function BL31 is loaded in memory and its entrypoint
+ * is set by load_image. This is a placeholder for the platform to change
+ * the entrypoint of BL31 and set SPSR and security state.
+ * On FVP we are only setting the security state, entrypoint
+ */
+void bl2_plat_bl31_post_load_actions(struct image_info *image,
+				     struct el_change_info *ep);
+
+/*
+ * Before calling this function BL32 is loaded in memory and its entrypoint
+ * is set by load_image. This is a placeholder for the platform to change
+ * the entrypoint of BL32 and set SPSR and security state.
+ * On FVP we are only setting the security state, entrypoint
+ */
+void bl2_plat_bl32_post_load_actions(struct image_info *image,
+				     struct el_change_info *ep);
+
+/*
+ * Before calling this function BL33 is loaded in memory and its entrypoint
+ * is set by load_image. This is a placeholder for the platform to change
+ * the entrypoint of BL33 and set SPSR and security state.
+ * On FVP we are only setting the security state, entrypoint
+ */
+void bl2_plat_bl33_post_load_actions(struct image_info *image,
+				     struct el_change_info *ep);
+
+/* Gets the memory layout for BL32 */
+void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
+
+/* Gets the memory layout for BL33 */
+void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
+
+
+#endif /* __PLATFORM_H__ */
diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c
index 48b07149be04c0c6725690fbfd4b2cb587c8161e..4e935a50e38c8316283c9e2235d64d192ebf8b87 100644
--- a/lib/aarch64/xlat_tables.c
+++ b/lib/aarch64/xlat_tables.c
@@ -29,7 +29,7 @@
  */
 
 #include <assert.h>
-#include <platform.h>
+#include <platform_def.h>
 #include <string.h>
 #include <xlat_tables.h>
 
diff --git a/lib/locks/bakery/bakery_lock.c b/lib/locks/bakery/bakery_lock.c
index 6d4ab87bb08501fc4bb4fff075a62584e543fe8d..4e148b5aab2107c23505ba6f55f3864d56960750 100644
--- a/lib/locks/bakery/bakery_lock.c
+++ b/lib/locks/bakery/bakery_lock.c
@@ -31,6 +31,7 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <bakery_lock.h>
+#include <platform.h>
 #include <string.h>
 
 /*
diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S
index 7e201213fe8b4ac01738d7a6fffbaac674e49d43..f6ac13ebb03a97a4e8f6627a563233368665af89 100644
--- a/plat/common/aarch64/platform_helpers.S
+++ b/plat/common/aarch64/platform_helpers.S
@@ -30,7 +30,7 @@
 
 #include <arch.h>
 #include <asm_macros.S>
-#include <platform.h>
+#include <platform_def.h>
 
 
 	.weak	platform_get_core_pos
diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S
index ebbf509b4b7b7b3c00bf8da237cd7f14a4e96316..801ec7fab62fcaa72e01df6255f3ccd50d29f96f 100644
--- a/plat/common/aarch64/platform_mp_stack.S
+++ b/plat/common/aarch64/platform_mp_stack.S
@@ -30,7 +30,7 @@
 
 #include <arch.h>
 #include <asm_macros.S>
-#include <platform.h>
+#include <platform_def.h>
 
 
 	.local	pcpu_dv_mem_stack
diff --git a/plat/common/aarch64/platform_up_stack.S b/plat/common/aarch64/platform_up_stack.S
index 880793d890c44450c6c9ed650dd1d71d03e6e570..45a96a6469d50a6def866ea9e05a57d2896b9d03 100644
--- a/plat/common/aarch64/platform_up_stack.S
+++ b/plat/common/aarch64/platform_up_stack.S
@@ -30,7 +30,7 @@
 
 #include <arch.h>
 #include <asm_macros.S>
-#include <platform.h>
+#include <platform_def.h>
 
 
 	.local	pcpu_dv_mem_stack
diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/plat_common.c
index 039197fae5dc1feb113717bdd65c71d8c53e7af2..a5a9291fb0dd6d23f3f1acca06034fe2469513a9 100644
--- a/plat/fvp/aarch64/plat_common.c
+++ b/plat/fvp/aarch64/plat_common.c
@@ -34,6 +34,7 @@
 #include <bl_common.h>
 #include <cci400.h>
 #include <debug.h>
+#include <fvp_def.h>
 #include <mmio.h>
 #include <platform.h>
 #include <xlat_tables.h>
diff --git a/plat/fvp/aarch64/plat_helpers.S b/plat/fvp/aarch64/plat_helpers.S
index 9b6b13aaea38a897e8350d6dc53d6a1b0d4f6789..f8976816bae746a2de2616a29cfa2d179a478aa8 100644
--- a/plat/fvp/aarch64/plat_helpers.S
+++ b/plat/fvp/aarch64/plat_helpers.S
@@ -31,8 +31,8 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <bl_common.h>
+#include <fvp_def.h>
 #include <gic_v2.h>
-#include <platform.h>
 #include "../drivers/pwrc/fvp_pwrc.h"
 
 	.globl	platform_get_entrypoint
diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c
index b69b2ab54be6e954356713f972d61346eb97733a..0173802f10ff8240110a4e88a5d517dae00c188f 100644
--- a/plat/fvp/bl1_plat_setup.c
+++ b/plat/fvp/bl1_plat_setup.c
@@ -33,8 +33,11 @@
 #include <bl_common.h>
 #include <bl1.h>
 #include <console.h>
+#include <fvp_def.h>
 #include <mmio.h>
 #include <platform.h>
+#include <platform_def.h>
+#include "fvp_private.h"
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c
index 41ca06fedcfd475615ac3f6152c7540bf4d23afa..ecc8c467ddc599c902105ba06b9da31a00c7841a 100644
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_plat_setup.c
@@ -33,8 +33,11 @@
 #include <bl_common.h>
 #include <bl2.h>
 #include <console.h>
+#include <fvp_def.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <string.h>
+#include "fvp_private.h"
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c
index 2e012ba0f5ed1936c2da23571c35cde521e4818f..4d6e0f599139bec59f00d7b1b5cd56bb7d138b9d 100644
--- a/plat/fvp/bl31_plat_setup.c
+++ b/plat/fvp/bl31_plat_setup.c
@@ -34,10 +34,12 @@
 #include <bl_common.h>
 #include <bl31.h>
 #include <console.h>
+#include <fvp_def.h>
 #include <mmio.h>
 #include <platform.h>
 #include <stddef.h>
 #include "drivers/pwrc/fvp_pwrc.h"
+#include "fvp_private.h"
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_plat_setup.c
index 772e972fa003c9107e7a045152b0e28c4c135bf2..3f82962a92b8e262b549610f7e4ad1d0c08eac9d 100644
--- a/plat/fvp/bl32_plat_setup.c
+++ b/plat/fvp/bl32_plat_setup.c
@@ -32,6 +32,8 @@
 #include <bl_common.h>
 #include <bl32.h>
 #include <console.h>
+#include <fvp_def.h>
+#include <fvp_private.h>
 #include <platform.h>
 
 /*******************************************************************************
diff --git a/plat/fvp/drivers/pwrc/fvp_pwrc.c b/plat/fvp/drivers/pwrc/fvp_pwrc.c
index 7a7f5168adfd95a4b62efadaab3f8b2e1f3e8640..9a08e42b21cd173cde5aa07dc087abb6932c1960 100644
--- a/plat/fvp/drivers/pwrc/fvp_pwrc.c
+++ b/plat/fvp/drivers/pwrc/fvp_pwrc.c
@@ -29,6 +29,7 @@
  */
 
 #include <bakery_lock.h>
+#include <fvp_def.h>
 #include <mmio.h>
 #include "fvp_pwrc.h"
 
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
new file mode 100644
index 0000000000000000000000000000000000000000..a25bc990ce097115387ee37471061c210cf9f5c7
--- /dev/null
+++ b/plat/fvp/fvp_def.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FVP_DEF_H__
+#define __FVP_DEF_H__
+
+#include <platform_def.h> /* for TZROM_SIZE */
+
+
+/* Firmware Image Package */
+#define FIP_IMAGE_NAME			"fip.bin"
+
+/* Constants for accessing platform configuration */
+#define CONFIG_GICD_ADDR		0
+#define CONFIG_GICC_ADDR		1
+#define CONFIG_GICH_ADDR		2
+#define CONFIG_GICV_ADDR		3
+#define CONFIG_MAX_AFF0		4
+#define CONFIG_MAX_AFF1		5
+/* Indicate whether the CPUECTLR SMP bit should be enabled. */
+#define CONFIG_CPU_SETUP		6
+#define CONFIG_BASE_MMAP		7
+/* Indicates whether CCI should be enabled on the platform. */
+#define CONFIG_HAS_CCI			8
+#define CONFIG_HAS_TZC			9
+#define CONFIG_LIMIT			10
+
+/*******************************************************************************
+ * FVP memory map related constants
+ ******************************************************************************/
+
+#define FLASH0_BASE		0x08000000
+#define FLASH0_SIZE		TZROM_SIZE
+
+#define FLASH1_BASE		0x0c000000
+#define FLASH1_SIZE		0x04000000
+
+#define PSRAM_BASE		0x14000000
+#define PSRAM_SIZE		0x04000000
+
+#define VRAM_BASE		0x18000000
+#define VRAM_SIZE		0x02000000
+
+/* Aggregate of all devices in the first GB */
+#define DEVICE0_BASE		0x1a000000
+#define DEVICE0_SIZE		0x12200000
+
+#define DEVICE1_BASE		0x2f000000
+#define DEVICE1_SIZE		0x200000
+
+#define NSRAM_BASE		0x2e000000
+#define NSRAM_SIZE		0x10000
+
+#define MBOX_OFF		0x1000
+
+/* Base address where parameters to BL31 are stored */
+#define PARAMS_BASE		TZDRAM_BASE
+
+#define DRAM1_BASE		0x80000000ull
+#define DRAM1_SIZE		0x80000000ull
+#define DRAM1_END		(DRAM1_BASE + DRAM1_SIZE - 1)
+#define DRAM1_SEC_SIZE		0x01000000ull
+
+#define DRAM_BASE		DRAM1_BASE
+#define DRAM_SIZE		DRAM1_SIZE
+
+#define DRAM2_BASE		0x880000000ull
+#define DRAM2_SIZE		0x780000000ull
+#define DRAM2_END		(DRAM2_BASE + DRAM2_SIZE - 1)
+
+#define PCIE_EXP_BASE		0x40000000
+#define TZRNG_BASE		0x7fe60000
+#define TZNVCTR_BASE		0x7fe70000
+#define TZROOTKEY_BASE		0x7fe80000
+
+/* Memory mapped Generic timer interfaces  */
+#define SYS_CNTCTL_BASE		0x2a430000
+#define SYS_CNTREAD_BASE	0x2a800000
+#define SYS_TIMCTL_BASE		0x2a810000
+
+/* Counter timer module offsets */
+#define CNTNSAR			0x4
+#define CNTNSAR_NS_SHIFT(x)	x
+
+#define CNTACR_BASE(x)		(0x40 + (x << 2))
+#define CNTACR_RPCT_SHIFT	0x0
+#define CNTACR_RVCT_SHIFT	0x1
+#define CNTACR_RFRQ_SHIFT	0x2
+#define CNTACR_RVOFF_SHIFT	0x3
+#define CNTACR_RWVT_SHIFT	0x4
+#define CNTACR_RWPT_SHIFT	0x5
+
+/* V2M motherboard system registers & offsets */
+#define VE_SYSREGS_BASE		0x1c010000
+#define V2M_SYS_ID			0x0
+#define V2M_SYS_LED			0x8
+#define V2M_SYS_CFGDATA		0xa0
+#define V2M_SYS_CFGCTRL		0xa4
+
+/*
+ * V2M sysled bit definitions. The values written to this
+ * register are defined in arch.h & runtime_svc.h. Only
+ * used by the primary cpu to diagnose any cold boot issues.
+ *
+ * SYS_LED[0]   - Security state (S=0/NS=1)
+ * SYS_LED[2:1] - Exception Level (EL3-EL0)
+ * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
+ *
+ */
+#define SYS_LED_SS_SHIFT		0x0
+#define SYS_LED_EL_SHIFT		0x1
+#define SYS_LED_EC_SHIFT		0x3
+
+#define SYS_LED_SS_MASK		0x1
+#define SYS_LED_EL_MASK		0x3
+#define SYS_LED_EC_MASK		0x1f
+
+/* V2M sysid register bits */
+#define SYS_ID_REV_SHIFT	27
+#define SYS_ID_HBI_SHIFT	16
+#define SYS_ID_BLD_SHIFT	12
+#define SYS_ID_ARCH_SHIFT	8
+#define SYS_ID_FPGA_SHIFT	0
+
+#define SYS_ID_REV_MASK	0xf
+#define SYS_ID_HBI_MASK	0xfff
+#define SYS_ID_BLD_MASK	0xf
+#define SYS_ID_ARCH_MASK	0xf
+#define SYS_ID_FPGA_MASK	0xff
+
+#define SYS_ID_BLD_LENGTH	4
+
+#define REV_FVP		0x0
+#define HBI_FVP_BASE		0x020
+#define HBI_FOUNDATION		0x010
+
+#define BLD_GIC_VE_MMAP	0x0
+#define BLD_GIC_A53A57_MMAP	0x1
+
+#define ARCH_MODEL		0x1
+
+/* FVP Power controller base address*/
+#define PWRC_BASE		0x1c100000
+
+/*******************************************************************************
+ * Platform specific per affinity states. Distinction between off and suspend
+ * is made to allow reporting of a suspended cpu as still being on e.g. in the
+ * affinity_info psci call.
+ ******************************************************************************/
+/* TODO: Check with Achin - these are not used anywhere */
+#define PLATFORM_MAX_AFF0	4
+#define PLATFORM_MAX_AFF1	2
+#define PLAT_AFF_UNK		0xff
+
+#define PLAT_AFF0_OFF		0x0
+#define PLAT_AFF0_ONPENDING	0x1
+#define PLAT_AFF0_SUSPEND	0x2
+#define PLAT_AFF0_ON		0x3
+
+#define PLAT_AFF1_OFF		0x0
+#define PLAT_AFF1_ONPENDING	0x1
+#define PLAT_AFF1_SUSPEND	0x2
+#define PLAT_AFF1_ON		0x3
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define ADDR_SPACE_SIZE			(1ull << 32)
+#define MAX_XLAT_TABLES			3
+#define MAX_MMAP_REGIONS		16
+
+
+/*******************************************************************************
+ * CCI-400 related constants
+ ******************************************************************************/
+#define CCI400_BASE			0x2c090000
+#define CCI400_SL_IFACE_CLUSTER0	3
+#define CCI400_SL_IFACE_CLUSTER1	4
+#define CCI400_SL_IFACE_INDEX(mpidr)	(mpidr & MPIDR_CLUSTER_MASK ? \
+					 CCI400_SL_IFACE_CLUSTER1 :   \
+					 CCI400_SL_IFACE_CLUSTER0)
+
+/*******************************************************************************
+ * GIC-400 & interrupt handling related constants
+ ******************************************************************************/
+/* VE compatible GIC memory map */
+#define VE_GICD_BASE			0x2c001000
+#define VE_GICC_BASE			0x2c002000
+#define VE_GICH_BASE			0x2c004000
+#define VE_GICV_BASE			0x2c006000
+
+/* Base FVP compatible GIC memory map */
+#define BASE_GICD_BASE			0x2f000000
+#define BASE_GICR_BASE			0x2f100000
+#define BASE_GICC_BASE			0x2c000000
+#define BASE_GICH_BASE			0x2c010000
+#define BASE_GICV_BASE			0x2c02f000
+
+#define IRQ_TZ_WDOG			56
+#define IRQ_SEC_PHY_TIMER		29
+#define IRQ_SEC_SGI_0			8
+#define IRQ_SEC_SGI_1			9
+#define IRQ_SEC_SGI_2			10
+#define IRQ_SEC_SGI_3			11
+#define IRQ_SEC_SGI_4			12
+#define IRQ_SEC_SGI_5			13
+#define IRQ_SEC_SGI_6			14
+#define IRQ_SEC_SGI_7			15
+#define IRQ_SEC_SGI_8			16
+
+/*******************************************************************************
+ * PL011 related constants
+ ******************************************************************************/
+#define PL011_UART0_BASE		0x1c090000
+#define PL011_UART1_BASE		0x1c0a0000
+#define PL011_UART2_BASE		0x1c0b0000
+#define PL011_UART3_BASE		0x1c0c0000
+
+/*******************************************************************************
+ * TrustZone address space controller related constants
+ ******************************************************************************/
+#define TZC400_BASE			0x2a4a0000
+
+/*
+ * The NSAIDs for this platform as used to program the TZC400.
+ */
+
+/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */
+#define FVP_AID_WIDTH			4
+
+/* NSAIDs used by devices in TZC filter 0 on FVP */
+#define FVP_NSAID_DEFAULT		0
+#define FVP_NSAID_PCI			1
+#define FVP_NSAID_VIRTIO		8  /* from FVP v5.6 onwards */
+#define FVP_NSAID_AP			9  /* Application Processors */
+#define FVP_NSAID_VIRTIO_OLD		15 /* until FVP v5.5 */
+
+/* NSAIDs used by devices in TZC filter 2 on FVP */
+#define FVP_NSAID_HDLCD0		2
+#define FVP_NSAID_CLCD			7
+
+
+#endif /* __FVP_DEF_H__ */
diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h
new file mode 100644
index 0000000000000000000000000000000000000000..efa1f75ce801d2b3122458bbe3bb00fad87c5f78
--- /dev/null
+++ b/plat/fvp/fvp_private.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FVP_PRIVATE_H__
+#define __FVP_PRIVATE_H__
+
+#include <bl_common.h>
+#include <platform_def.h>
+
+
+typedef volatile struct mailbox {
+	unsigned long value
+	__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
+} mailbox_t;
+
+/*******************************************************************************
+ * This structure represents the superset of information that is passed to
+ * BL31 e.g. while passing control to it from BL2 which is bl31_params
+ * and bl31_plat_params and its elements
+ ******************************************************************************/
+typedef struct bl2_to_bl31_params_mem {
+	bl31_params_t bl31_params;
+	image_info_t bl31_image;
+	image_info_t bl32_image;
+	image_info_t bl33_image;
+	el_change_info_t bl33_ep;
+	el_change_info_t bl32_ep;
+	el_change_info_t bl31_ep;
+} bl2_to_bl31_params_mem_t;
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+unsigned long platform_get_cfgvar(unsigned int);
+int platform_config_setup(void);
+
+#if RESET_TO_BL31
+void plat_get_entry_point_info(unsigned long target_security,
+				el_change_info_t *target_entry_info);
+#endif
+void plat_cci_setup(void);
+
+/* Declarations for fvp_gic.c */
+void gic_cpuif_deactivate(unsigned int);
+void gic_cpuif_setup(unsigned int);
+void gic_pcpu_distif_setup(unsigned int);
+void gic_setup(void);
+
+/* Declarations for fvp_topology.c */
+int plat_setup_topology(void);
+
+/* Declarations for plat_io_storage.c */
+void io_setup(void);
+
+/* Declarations for plat_security.c */
+void plat_security_setup(void);
+
+/* Sets the entrypoint  for BL32 */
+void fvp_set_bl32_entrypoint(el_change_info_t *bl32_ep);
+
+/* Sets the entrypoint  for BL33 */
+void fvp_set_bl33_entrypoint(el_change_info_t *bl33_ep);
+
+
+#endif /* __FVP_PRIVATE_H__ */
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index 0b9b2e2669d415e006f93322a89654a02d370d3e..4f181dbfff24ede7d39ec89ed366a464cd58d0e4 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -28,8 +28,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <fvp_def.h>
 #include <gic_v2.h>
-#include <platform.h>
 
 .section .rodata.gic_reg_name, "aS"
 gic_regs: .asciz "gic_iar", "gic_ctlr", ""
diff --git a/plat/fvp/plat_gic.c b/plat/fvp/plat_gic.c
index 7dec404f8e0e4fb52702e88ff6442de43afe44fd..bbcd418579e3b68125bf20f60fce9c5279719625 100644
--- a/plat/fvp/plat_gic.c
+++ b/plat/fvp/plat_gic.c
@@ -32,11 +32,13 @@
 #include <assert.h>
 #include <bl_common.h>
 #include <debug.h>
+#include <fvp_def.h>
 #include <gic_v2.h>
 #include <gic_v3.h>
 #include <interrupt_mgmt.h>
 #include <platform.h>
 #include <stdint.h>
+#include "fvp_private.h"
 
 /*******************************************************************************
  * This function does some minimal GICv3 configuration. The Firmware itself does
diff --git a/plat/fvp/plat_io_storage.c b/plat/fvp/plat_io_storage.c
index aac8a9604f9f8995d64b168b82178ab95f7d6981..0a034edbc7888d7a9fb6b65d0c75fcb323ccb6a5 100644
--- a/plat/fvp/plat_io_storage.c
+++ b/plat/fvp/plat_io_storage.c
@@ -35,7 +35,7 @@
 #include <io_memmap.h>
 #include <io_storage.h>
 #include <io_semihosting.h>
-#include <platform.h>
+#include <fvp_def.h>
 #include <semihosting.h>	/* For FOPEN_MODE_... */
 #include <string.h>
 
diff --git a/plat/fvp/plat_pm.c b/plat/fvp/plat_pm.c
index 459d6221b4920e152f47ce2495e8f2efa42ed7c7..5a88e87f39921f40ef0b9ea7e0b40c80533a378c 100644
--- a/plat/fvp/plat_pm.c
+++ b/plat/fvp/plat_pm.c
@@ -32,10 +32,13 @@
 #include <assert.h>
 #include <bakery_lock.h>
 #include <cci400.h>
+#include <fvp_def.h>
 #include <mmio.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <psci.h>
 #include "drivers/pwrc/fvp_pwrc.h"
+#include "fvp_private.h"
 
 /*******************************************************************************
  * FVP handler called when an affinity instance is about to enter standby.
diff --git a/plat/fvp/plat_security.c b/plat/fvp/plat_security.c
index 9da56122035a3be5c50414ba23e5aec9e2ba4f90..79dabe2a1045ed140ac6b9f0c4c2aab625b67c35 100644
--- a/plat/fvp/plat_security.c
+++ b/plat/fvp/plat_security.c
@@ -29,9 +29,10 @@
  */
 
 #include <assert.h>
-#include <platform.h>
-#include <tzc400.h>
 #include <debug.h>
+#include <fvp_def.h>
+#include <tzc400.h>
+#include "fvp_private.h"
 
 /* Used to improve readability for configuring regions. */
 #define FILTER_SHIFT(filter)	(1 << filter)
diff --git a/plat/fvp/plat_topology.c b/plat/fvp/plat_topology.c
index 04b409ecb158c333d6b4fc84e61c847daf6ed3c9..f06b4f7470653b123b97f9af9c9ca9223ce10a09 100644
--- a/plat/fvp/plat_topology.c
+++ b/plat/fvp/plat_topology.c
@@ -29,7 +29,7 @@
  */
 
 #include <assert.h>
-#include <platform.h>
+#include <platform_def.h>
 /* TODO: Reusing psci error codes & state information. Get our own! */
 #include <psci.h>
 #include "drivers/pwrc/fvp_pwrc.h"
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
deleted file mode 100644
index 0eb12489378d5a69d3c6553c110e3503eadef184..0000000000000000000000000000000000000000
--- a/plat/fvp/platform.h
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
-
-#include <arch.h>
-#include <bl_common.h>
-
-
-/*******************************************************************************
- * Platform binary types for linking
- ******************************************************************************/
-#define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH            aarch64
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
-
-/* Size of cacheable stacks */
-#define PLATFORM_STACK_SIZE	0x800
-
-/* Size of coherent stacks for debug and release builds */
-#if DEBUG
-#define PCPU_DV_MEM_STACK_SIZE	0x400
-#else
-#define PCPU_DV_MEM_STACK_SIZE	0x300
-#endif
-
-#define FIRMWARE_WELCOME_STR		"Booting trusted firmware boot loader stage 1\n\r"
-
-/* Trusted Boot Firmware BL2 */
-#define BL2_IMAGE_NAME			"bl2.bin"
-
-/* EL3 Runtime Firmware BL31 */
-#define BL31_IMAGE_NAME			"bl31.bin"
-
-/* Secure Payload BL32 (Trusted OS) */
-#define BL32_IMAGE_NAME			"bl32.bin"
-
-/* Non-Trusted Firmware BL33 and its load address */
-#define BL33_IMAGE_NAME			"bl33.bin" /* e.g. UEFI */
-#define NS_IMAGE_OFFSET			(DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
-
-/* Firmware Image Package */
-#define FIP_IMAGE_NAME			"fip.bin"
-
-#define PLATFORM_CACHE_LINE_SIZE	64
-#define PLATFORM_CLUSTER_COUNT		2ull
-#define PLATFORM_CLUSTER0_CORE_COUNT	4
-#define PLATFORM_CLUSTER1_CORE_COUNT	4
-#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
-						PLATFORM_CLUSTER0_CORE_COUNT)
-#define PLATFORM_MAX_CPUS_PER_CLUSTER	4
-#define PRIMARY_CPU			0x0
-#define MAX_IO_DEVICES			3
-#define MAX_IO_HANDLES			4
-
-/* Constants for accessing platform configuration */
-#define CONFIG_GICD_ADDR		0
-#define CONFIG_GICC_ADDR		1
-#define CONFIG_GICH_ADDR		2
-#define CONFIG_GICV_ADDR		3
-#define CONFIG_MAX_AFF0		4
-#define CONFIG_MAX_AFF1		5
-/* Indicate whether the CPUECTLR SMP bit should be enabled. */
-#define CONFIG_CPU_SETUP		6
-#define CONFIG_BASE_MMAP		7
-/* Indicates whether CCI should be enabled on the platform. */
-#define CONFIG_HAS_CCI			8
-#define CONFIG_HAS_TZC			9
-#define CONFIG_LIMIT			10
-
-/*******************************************************************************
- * Platform memory map related constants
- ******************************************************************************/
-#define TZROM_BASE		0x00000000
-#define TZROM_SIZE		0x04000000
-
-#define TZRAM_BASE		0x04000000
-#define TZRAM_SIZE		0x40000
-
-#define FLASH0_BASE		0x08000000
-#define FLASH0_SIZE		TZROM_SIZE
-
-#define FLASH1_BASE		0x0c000000
-#define FLASH1_SIZE		0x04000000
-
-#define PSRAM_BASE		0x14000000
-#define PSRAM_SIZE		0x04000000
-
-#define VRAM_BASE		0x18000000
-#define VRAM_SIZE		0x02000000
-
-/* Aggregate of all devices in the first GB */
-#define DEVICE0_BASE		0x1a000000
-#define DEVICE0_SIZE		0x12200000
-
-#define DEVICE1_BASE		0x2f000000
-#define DEVICE1_SIZE		0x200000
-
-#define NSRAM_BASE		0x2e000000
-#define NSRAM_SIZE		0x10000
-
-/* Location of trusted dram on the base fvp */
-#define TZDRAM_BASE		0x06000000
-#define TZDRAM_SIZE		0x02000000
-#define MBOX_OFF		0x1000
-
-/* Base address where parameters to BL31 are stored */
-#define PARAMS_BASE		TZDRAM_BASE
-
-
-#define DRAM1_BASE		0x80000000ull
-#define DRAM1_SIZE		0x80000000ull
-#define DRAM1_END		(DRAM1_BASE + DRAM1_SIZE - 1)
-#define DRAM1_SEC_SIZE		0x01000000ull
-
-#define DRAM_BASE		DRAM1_BASE
-#define DRAM_SIZE		DRAM1_SIZE
-
-#define DRAM2_BASE		0x880000000ull
-#define DRAM2_SIZE		0x780000000ull
-#define DRAM2_END		(DRAM2_BASE + DRAM2_SIZE - 1)
-
-#define PCIE_EXP_BASE		0x40000000
-#define TZRNG_BASE		0x7fe60000
-#define TZNVCTR_BASE		0x7fe70000
-#define TZROOTKEY_BASE		0x7fe80000
-
-/* Memory mapped Generic timer interfaces  */
-#define SYS_CNTCTL_BASE		0x2a430000
-#define SYS_CNTREAD_BASE	0x2a800000
-#define SYS_TIMCTL_BASE		0x2a810000
-
-/* Counter timer module offsets */
-#define CNTNSAR			0x4
-#define CNTNSAR_NS_SHIFT(x)	x
-
-#define CNTACR_BASE(x)		(0x40 + (x << 2))
-#define CNTACR_RPCT_SHIFT	0x0
-#define CNTACR_RVCT_SHIFT	0x1
-#define CNTACR_RFRQ_SHIFT	0x2
-#define CNTACR_RVOFF_SHIFT	0x3
-#define CNTACR_RWVT_SHIFT	0x4
-#define CNTACR_RWPT_SHIFT	0x5
-
-/* V2M motherboard system registers & offsets */
-#define VE_SYSREGS_BASE		0x1c010000
-#define V2M_SYS_ID			0x0
-#define V2M_SYS_LED			0x8
-#define V2M_SYS_CFGDATA		0xa0
-#define V2M_SYS_CFGCTRL		0xa4
-
-/*
- * V2M sysled bit definitions. The values written to this
- * register are defined in arch.h & runtime_svc.h. Only
- * used by the primary cpu to diagnose any cold boot issues.
- *
- * SYS_LED[0]   - Security state (S=0/NS=1)
- * SYS_LED[2:1] - Exception Level (EL3-EL0)
- * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
- *
- */
-#define SYS_LED_SS_SHIFT		0x0
-#define SYS_LED_EL_SHIFT		0x1
-#define SYS_LED_EC_SHIFT		0x3
-
-#define SYS_LED_SS_MASK		0x1
-#define SYS_LED_EL_MASK		0x3
-#define SYS_LED_EC_MASK		0x1f
-
-/* V2M sysid register bits */
-#define SYS_ID_REV_SHIFT	27
-#define SYS_ID_HBI_SHIFT	16
-#define SYS_ID_BLD_SHIFT	12
-#define SYS_ID_ARCH_SHIFT	8
-#define SYS_ID_FPGA_SHIFT	0
-
-#define SYS_ID_REV_MASK	0xf
-#define SYS_ID_HBI_MASK	0xfff
-#define SYS_ID_BLD_MASK	0xf
-#define SYS_ID_ARCH_MASK	0xf
-#define SYS_ID_FPGA_MASK	0xff
-
-#define SYS_ID_BLD_LENGTH	4
-
-#define REV_FVP		0x0
-#define HBI_FVP_BASE		0x020
-#define HBI_FOUNDATION		0x010
-
-#define BLD_GIC_VE_MMAP	0x0
-#define BLD_GIC_A53A57_MMAP	0x1
-
-#define ARCH_MODEL		0x1
-
-/* FVP Power controller base address*/
-#define PWRC_BASE		0x1c100000
-
-/*******************************************************************************
- * Platform specific per affinity states. Distinction between off and suspend
- * is made to allow reporting of a suspended cpu as still being on e.g. in the
- * affinity_info psci call.
- ******************************************************************************/
-#define PLATFORM_MAX_AFF0	4
-#define PLATFORM_MAX_AFF1	2
-#define PLAT_AFF_UNK		0xff
-
-#define PLAT_AFF0_OFF		0x0
-#define PLAT_AFF0_ONPENDING	0x1
-#define PLAT_AFF0_SUSPEND	0x2
-#define PLAT_AFF0_ON		0x3
-
-#define PLAT_AFF1_OFF		0x0
-#define PLAT_AFF1_ONPENDING	0x1
-#define PLAT_AFF1_SUSPEND	0x2
-#define PLAT_AFF1_ON		0x3
-
-/*******************************************************************************
- * BL2 specific defines.
- ******************************************************************************/
-#define BL2_BASE			(TZRAM_BASE + TZRAM_SIZE - 0xc000)
-
-/*******************************************************************************
- * BL31 specific defines.
- ******************************************************************************/
-#define BL31_BASE			(TZRAM_BASE + 0x6000)
-
-/*******************************************************************************
- * BL32 specific defines.
- ******************************************************************************/
-/*
- * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
- */
-#define TSP_IN_TZRAM			0
-#define TSP_IN_TZDRAM			1
-
-#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
-# define TSP_SEC_MEM_BASE		TZRAM_BASE
-# define TSP_SEC_MEM_SIZE		TZRAM_SIZE
-# define BL32_BASE			(TZRAM_BASE + TZRAM_SIZE - 0x1c000)
-# define BL32_LIMIT			BL2_BASE
-#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
-# define TSP_SEC_MEM_BASE		TZDRAM_BASE
-# define TSP_SEC_MEM_SIZE		TZDRAM_SIZE
-# define BL32_BASE			(TZDRAM_BASE + 0x2000)
-# define BL32_LIMIT			(TZDRAM_BASE + (1 << 21))
-#else
-# error "Unsupported TSP_RAM_LOCATION_ID value"
-#endif
-
-/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define ADDR_SPACE_SIZE			(1ull << 32)
-#define MAX_XLAT_TABLES			3
-#define MAX_MMAP_REGIONS		16
-
-
-/*******************************************************************************
- * CCI-400 related constants
- ******************************************************************************/
-#define CCI400_BASE			0x2c090000
-#define CCI400_SL_IFACE_CLUSTER0	3
-#define CCI400_SL_IFACE_CLUSTER1	4
-#define CCI400_SL_IFACE_INDEX(mpidr)	(mpidr & MPIDR_CLUSTER_MASK ? \
-					 CCI400_SL_IFACE_CLUSTER1 :   \
-					 CCI400_SL_IFACE_CLUSTER0)
-
-/*******************************************************************************
- * GIC-400 & interrupt handling related constants
- ******************************************************************************/
-/* VE compatible GIC memory map */
-#define VE_GICD_BASE			0x2c001000
-#define VE_GICC_BASE			0x2c002000
-#define VE_GICH_BASE			0x2c004000
-#define VE_GICV_BASE			0x2c006000
-
-/* Base FVP compatible GIC memory map */
-#define BASE_GICD_BASE			0x2f000000
-#define BASE_GICR_BASE			0x2f100000
-#define BASE_GICC_BASE			0x2c000000
-#define BASE_GICH_BASE			0x2c010000
-#define BASE_GICV_BASE			0x2c02f000
-
-#define IRQ_TZ_WDOG			56
-#define IRQ_SEC_PHY_TIMER		29
-#define IRQ_SEC_SGI_0			8
-#define IRQ_SEC_SGI_1			9
-#define IRQ_SEC_SGI_2			10
-#define IRQ_SEC_SGI_3			11
-#define IRQ_SEC_SGI_4			12
-#define IRQ_SEC_SGI_5			13
-#define IRQ_SEC_SGI_6			14
-#define IRQ_SEC_SGI_7			15
-#define IRQ_SEC_SGI_8			16
-
-/*******************************************************************************
- * PL011 related constants
- ******************************************************************************/
-#define PL011_UART0_BASE		0x1c090000
-#define PL011_UART1_BASE		0x1c0a0000
-#define PL011_UART2_BASE		0x1c0b0000
-#define PL011_UART3_BASE		0x1c0c0000
-
-
-/*******************************************************************************
- * TrustZone address space controller related constants
- ******************************************************************************/
-#define TZC400_BASE			0x2a4a0000
-
-/*
- * The NSAIDs for this platform as used to program the TZC400.
- */
-
-/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */
-#define FVP_AID_WIDTH			4
-
-/* NSAIDs used by devices in TZC filter 0 on FVP */
-#define FVP_NSAID_DEFAULT		0
-#define FVP_NSAID_PCI			1
-#define FVP_NSAID_VIRTIO		8  /* from FVP v5.6 onwards */
-#define FVP_NSAID_AP			9  /* Application Processors */
-#define FVP_NSAID_VIRTIO_OLD		15 /* until FVP v5.5 */
-
-/* NSAIDs used by devices in TZC filter 2 on FVP */
-#define FVP_NSAID_HDLCD0		2
-#define FVP_NSAID_CLCD			7
-
-
-/*******************************************************************************
- * Declarations and constants to access the mailboxes safely. Each mailbox is
- * aligned on the biggest cache line size in the platform. This is known only
- * to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two maiboxes do not sit on the same cache
- * line at any cache level. They could belong to different cpus/clusters &
- * get written while being protected by different locks causing corruption of
- * a valid mailbox address.
- ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT   6
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-#ifndef __ASSEMBLY__
-
-#include <stdint.h>
-#include <bl_common.h>
-
-
-typedef volatile struct mailbox {
-	unsigned long value
-	__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
-} mailbox_t;
-
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31 e.g. while passing control to it from BL2 which is bl31_params
- * and bl31_plat_params and its elements
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
-	bl31_params_t bl31_params;
-	image_info_t bl31_image;
-	image_info_t bl32_image;
-	image_info_t bl33_image;
-	el_change_info_t bl33_ep;
-	el_change_info_t bl32_ep;
-	el_change_info_t bl31_ep;
-} bl2_to_bl31_params_mem_t;
-
-
-/*******************************************************************************
- * Forward declarations
- ******************************************************************************/
-struct plat_pm_ops;
-struct meminfo;
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void bl1_plat_arch_setup(void);
-void bl2_plat_arch_setup(void);
-void bl31_plat_arch_setup(void);
-int platform_setup_pm(const struct plat_pm_ops **);
-unsigned int platform_get_core_pos(unsigned long mpidr);
-void enable_mmu_el1(void);
-void enable_mmu_el3(void);
-void configure_mmu_el1(unsigned long total_base,
-		       unsigned long total_size,
-		       unsigned long ro_start,
-		       unsigned long ro_limit,
-		       unsigned long coh_start,
-		       unsigned long coh_limit);
-void configure_mmu_el3(unsigned long total_base,
-		       unsigned long total_size,
-		       unsigned long ro_start,
-		       unsigned long ro_limit,
-		       unsigned long coh_start,
-		       unsigned long coh_limit);
-unsigned long platform_get_cfgvar(unsigned int);
-int platform_config_setup(void);
-void plat_report_exception(unsigned long);
-unsigned long plat_get_ns_image_entrypoint(void);
-unsigned long platform_get_stack(unsigned long mpidr);
-uint64_t plat_get_syscnt_freq(void);
-#if RESET_TO_BL31
-void plat_get_entry_point_info(unsigned long target_security,
-				el_change_info_t *target_entry_info);
-#endif
-void plat_cci_setup(void);
-
-/* Declarations for plat_gic.c */
-uint32_t ic_get_pending_interrupt_id(void);
-uint32_t ic_get_pending_interrupt_type(void);
-uint32_t ic_acknowledge_interrupt(void);
-uint32_t ic_get_interrupt_type(uint32_t id);
-void ic_end_of_interrupt(uint32_t id);
-void gic_cpuif_deactivate(unsigned int);
-void gic_cpuif_setup(unsigned int);
-void gic_pcpu_distif_setup(unsigned int);
-void gic_setup(void);
-uint32_t plat_interrupt_type_to_line(uint32_t type,
-					    uint32_t security_state);
-
-/* Declarations for plat_topology.c */
-int plat_setup_topology(void);
-int plat_get_max_afflvl(void);
-unsigned int plat_get_aff_count(unsigned int, unsigned long);
-unsigned int plat_get_aff_state(unsigned int, unsigned long);
-
-/* Declarations for plat_io_storage.c */
-void io_setup(void);
-int plat_get_image_source(const char *image_name,
-			uintptr_t *dev_handle,
-			uintptr_t *image_spec);
-
-/* Declarations for plat_security.c */
-void plat_security_setup(void);
-
-/*
- * Before calling this function BL2 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL2 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- */
-void bl1_plat_bl2_loaded(image_info_t *image, el_change_info_t *ep);
-
-/*
- * Before calling this function BL31 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL31 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- */
-void bl2_plat_bl31_post_load_actions(image_info_t *image,
-					el_change_info_t *ep);
-
-/*
- * Before calling this function BL32 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- */
-void bl2_plat_bl32_post_load_actions(image_info_t *image,
-					el_change_info_t *ep);
-
-/*
- * Before calling this function BL33 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL33 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- */
-void bl2_plat_bl33_post_load_actions(image_info_t *image,
-					el_change_info_t *ep);
-
-/* Gets the memory layout for BL32 */
-void bl2_plat_get_bl32_meminfo(meminfo_t *mem_info);
-
-/* Gets the memory layout for BL33 */
-void bl2_plat_get_bl33_meminfo(meminfo_t *mem_info);
-
-/* Sets the entrypoint  for BL32 */
-void fvp_set_bl32_entrypoint(el_change_info_t *bl32_ep);
-
-/* Sets the entrypoint  for BL33 */
-void fvp_set_bl33_entrypoint(el_change_info_t *bl33_ep);
-
-
-#endif /*__ASSEMBLY__*/
-
-#endif /* __PLATFORM_H__ */
diff --git a/plat/fvp/platform_def.h b/plat/fvp/platform_def.h
new file mode 100644
index 0000000000000000000000000000000000000000..a888c1e28803f073108dee07f8ff765415a2e4ef
--- /dev/null
+++ b/plat/fvp/platform_def.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arch.h>
+
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH            aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Size of cacheable stacks */
+#define PLATFORM_STACK_SIZE	0x800
+
+/* Size of coherent stacks for debug and release builds */
+#if DEBUG
+#define PCPU_DV_MEM_STACK_SIZE	0x400
+#else
+#define PCPU_DV_MEM_STACK_SIZE	0x300
+#endif
+
+#define FIRMWARE_WELCOME_STR		"Booting trusted firmware boot loader stage 1\n\r"
+
+/* Trusted Boot Firmware BL2 */
+#define BL2_IMAGE_NAME			"bl2.bin"
+
+/* EL3 Runtime Firmware BL31 */
+#define BL31_IMAGE_NAME			"bl31.bin"
+
+/* Secure Payload BL32 (Trusted OS) */
+#define BL32_IMAGE_NAME			"bl32.bin"
+
+/* Non-Trusted Firmware BL33 and its load address */
+#define BL33_IMAGE_NAME			"bl33.bin" /* e.g. UEFI */
+#define NS_IMAGE_OFFSET			(DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
+
+#define PLATFORM_CACHE_LINE_SIZE	64
+#define PLATFORM_CLUSTER_COUNT		2ull
+#define PLATFORM_CLUSTER0_CORE_COUNT	4
+#define PLATFORM_CLUSTER1_CORE_COUNT	4
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
+						PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	4
+#define PRIMARY_CPU			0x0
+#define MAX_IO_DEVICES			3
+#define MAX_IO_HANDLES			4
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define TZROM_BASE		0x00000000
+#define TZROM_SIZE		0x04000000
+
+#define TZRAM_BASE		0x04000000
+#define TZRAM_SIZE		0x40000
+
+/* Location of trusted dram on the base fvp */
+#define TZDRAM_BASE		0x06000000
+#define TZDRAM_SIZE		0x02000000
+
+/*******************************************************************************
+ * BL2 specific defines.
+ ******************************************************************************/
+#define BL2_BASE			(TZRAM_BASE + TZRAM_SIZE - 0xc000)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+#define BL31_BASE			(TZRAM_BASE + 0x6000)
+
+/*******************************************************************************
+ * BL32 specific defines.
+ ******************************************************************************/
+/*
+ * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
+ */
+#define TSP_IN_TZRAM			0
+#define TSP_IN_TZDRAM			1
+
+#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
+# define TSP_SEC_MEM_BASE		TZRAM_BASE
+# define TSP_SEC_MEM_SIZE		TZRAM_SIZE
+# define BL32_BASE			(TZRAM_BASE + TZRAM_SIZE - 0x1c000)
+# define BL32_LIMIT			BL2_BASE
+#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
+# define TSP_SEC_MEM_BASE		TZDRAM_BASE
+# define TSP_SEC_MEM_SIZE		TZDRAM_SIZE
+# define BL32_BASE			(TZDRAM_BASE + 0x2000)
+# define BL32_LIMIT			(TZDRAM_BASE + (1 << 21))
+#else
+# error "Unsupported TSP_RAM_LOCATION_ID value"
+#endif
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define ADDR_SPACE_SIZE			(1ull << 32)
+#define MAX_XLAT_TABLES			3
+#define MAX_MMAP_REGIONS		16
+
+
+/*******************************************************************************
+ * CCI-400 related constants
+ ******************************************************************************/
+#define CCI400_BASE			0x2c090000
+#define CCI400_SL_IFACE_CLUSTER0	3
+#define CCI400_SL_IFACE_CLUSTER1	4
+#define CCI400_SL_IFACE_INDEX(mpidr)	(mpidr & MPIDR_CLUSTER_MASK ? \
+					 CCI400_SL_IFACE_CLUSTER1 :   \
+					 CCI400_SL_IFACE_CLUSTER0)
+
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT   6
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/services/spd/tspd/tspd_common.c b/services/spd/tspd/tspd_common.c
index 2ca6a56af2b7fb3a7485c76c892b459e23c52374..6b3592e3f0ff8ba4bc553816f1b419bf96861dd6 100644
--- a/services/spd/tspd/tspd_common.c
+++ b/services/spd/tspd/tspd_common.c
@@ -32,7 +32,6 @@
 #include <assert.h>
 #include <bl_common.h>
 #include <context_mgmt.h>
-#include <platform.h>
 #include <string.h>
 #include "tspd_private.h"
 
diff --git a/services/spd/tspd/tspd_pm.c b/services/spd/tspd/tspd_pm.c
index 2f204494529319e68c458a9df1df827e7f961828..ec4989df1964db1b2e784803d2ece653407759ef 100644
--- a/services/spd/tspd/tspd_pm.c
+++ b/services/spd/tspd/tspd_pm.c
@@ -33,6 +33,7 @@
 #include <bl_common.h>
 #include <context_mgmt.h>
 #include <debug.h>
+#include <platform.h>
 #include <tsp.h>
 #include "tspd_private.h"
 
diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h
index fb71922512921ee72c45f047710067f36374854d..5d7bf4b6f4f3c88909b3d4846821348734fbfdd2 100644
--- a/services/spd/tspd/tspd_private.h
+++ b/services/spd/tspd/tspd_private.h
@@ -34,7 +34,7 @@
 #include <arch.h>
 #include <context.h>
 #include <interrupt_mgmt.h>
-#include <platform.h>
+#include <platform_def.h>
 #include <psci.h>
 
 /*******************************************************************************
diff --git a/services/std_svc/psci/psci_afflvl_on.c b/services/std_svc/psci/psci_afflvl_on.c
index 360b2860f49fd8a25d7487759c8e510f601cd096..1e5828caca24b60de4e8b47c771de4f38dab691a 100644
--- a/services/std_svc/psci/psci_afflvl_on.c
+++ b/services/std_svc/psci/psci_afflvl_on.c
@@ -34,6 +34,7 @@
 #include <bl_common.h>
 #include <bl31.h>
 #include <context_mgmt.h>
+#include <platform.h>
 #include <runtime_svc.h>
 #include <stddef.h>
 #include "psci_private.h"
diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c
index 025d8b434a8d95e3bf3edf53a26b655aa318eef8..7edbdd6d96057bdad0eb2c0cbdee996bd2ed705b 100644
--- a/services/std_svc/psci/psci_common.c
+++ b/services/std_svc/psci/psci_common.c
@@ -35,6 +35,7 @@
 #include <context.h>
 #include <context_mgmt.h>
 #include <debug.h>
+#include <platform.h>
 #include "psci_private.h"
 
 /*