Commit e31d76fd authored by Jeenu Viswambharan's avatar Jeenu Viswambharan
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docs: Add Exception Handling Framework documentation



Change-Id: I77d38758d18ba6dda1652b1b1e644fbfb14386cc
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
parent 90a9213b
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...@@ -981,6 +981,11 @@ services ``handle()`` function. ...@@ -981,6 +981,11 @@ services ``handle()`` function.
On return from the handler the result registers are populated in X0-X3 before On return from the handler the result registers are populated in X0-X3 before
restoring the stack and CPU state and returning from the original SMC. restoring the stack and CPU state and returning from the original SMC.
Exception Handling Framework
----------------------------
Please refer to the `Exception Handling Framework`_ document.
Power State Coordination Interface Power State Coordination Interface
---------------------------------- ----------------------------------
...@@ -2641,5 +2646,6 @@ References ...@@ -2641,5 +2646,6 @@ References
.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf .. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
.. _TF-A Interrupt Management Design guide: ./interrupt-framework-design.rst .. _TF-A Interrupt Management Design guide: ./interrupt-framework-design.rst
.. _Xlat_tables design: xlat-tables-lib-v2-design.rst .. _Xlat_tables design: xlat-tables-lib-v2-design.rst
.. _Exception Handling Framework: exception-handling.rst
.. |Image 1| image:: diagrams/rt-svc-descs-layout.png?raw=true .. |Image 1| image:: diagrams/rt-svc-descs-layout.png?raw=true
...@@ -153,7 +153,10 @@ EL3 interrupts ...@@ -153,7 +153,10 @@ EL3 interrupts
However, when ``EL3_EXCEPTION_HANDLING`` is ``1``, this routing model is However, when ``EL3_EXCEPTION_HANDLING`` is ``1``, this routing model is
invalid as EL3 interrupts are unconditionally routed to EL3, and EL3 invalid as EL3 interrupts are unconditionally routed to EL3, and EL3
interrupts will always preempt Secure EL1/EL0 execution. interrupts will always preempt Secure EL1/EL0 execution. See `exception
handling`__ documentation.
.. __: exception-handling.rst#interrupt-handling
#. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in #. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in
Secure-EL1/Secure-EL0. This is a valid routing model as secure software Secure-EL1/Secure-EL0. This is a valid routing model as secure software
......
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