diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index 1486b9807bb68be6cff86b2feb4db6c26a65984a..9afcfd8a116188e569b8cbadb83a41f4d35ae5fd 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -6,6 +6,7 @@ #ifndef __CORTEX_A57_H__ #define __CORTEX_A57_H__ +#include <utils_def.h> /* Cortex-A57 midr for revision 0 */ #define CORTEX_A57_MIDR 0x410FD070 @@ -24,13 +25,13 @@ ******************************************************************************/ #define CORTEX_A57_ECTLR p15, 1, c15 -#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6) -#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 -#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. @@ -42,26 +43,26 @@ ******************************************************************************/ #define CORTEX_A57_ACTLR p15, 0, c15 -#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59) -#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54) -#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52) -#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49) -#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44) -#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38) -#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27) -#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25) -#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) +#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) +#define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52) +#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25) +#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 +#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 -#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Extended Control register specific definitions. @@ -69,7 +70,7 @@ #define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3 #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 -#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index 59057bc5a3f2b2650385ade9daf3118591c5871f..ed406ef0265befeaacf3967ca53cc99e3f16ea29 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -6,6 +6,7 @@ #ifndef __CORTEX_A72_H__ #define __CORTEX_A72_H__ +#include <utils_def.h> /* Cortex-A72 midr for revision 0 */ #define CORTEX_A72_MIDR 0x410FD080 @@ -13,42 +14,42 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_ECTLR p15, 1, c15 +#define CORTEX_A72_ECTLR p15, 1, c15 -#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6) -#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A72_MERRSR p15, 2, c15 +#define CORTEX_A72_MERRSR p15, 2, c15 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_ACTLR p15, 0, c15 +#define CORTEX_A72_ACTLR p15, 0, c15 -#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) -#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49) -#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) +#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A72_ACTLR_DCC_AS_DCCI (ULL(1) << 44) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 +#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 -#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2MERRSR p15, 3, c15 +#define CORTEX_A72_L2MERRSR p15, 3, c15 #endif /* __CORTEX_A72_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 20d11e14df04119fa763428496153fea9918d72c..e9788ffc05815eb655c5159079ac9802de075af8 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -6,6 +6,7 @@ #ifndef __CORTEX_A57_H__ #define __CORTEX_A57_H__ +#include <utils_def.h> /* Cortex-A57 midr for revision 0 */ #define CORTEX_A57_MIDR U(0x410FD070) @@ -55,15 +56,15 @@ /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 +#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) -#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) -#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) -#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) -#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) +#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) /******************************************************************************* * L2 Extended Control register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 90f0abd96e7e05d4294c78218dd42938e90e444d..a30abe8ec8a5d8ee8bd7c035ace1d53dd759b231 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -6,49 +6,50 @@ #ifndef __CORTEX_A72_H__ #define __CORTEX_A72_H__ +#include <utils_def.h> /* Cortex-A72 midr for revision 0 */ -#define CORTEX_A72_MIDR 0x410FD080 +#define CORTEX_A72_MIDR 0x410FD080 /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 +#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6) -#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 +#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0 +#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0 -#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) -#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49) -#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) +#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A72_ACTLR_DCC_AS_DCCI (ULL(1) << 44) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 +#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 +#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 #endif /* __CORTEX_A72_H__ */