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Commit e9cd36f5 authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration 

* changes:
  renesas: rzg: Add support to identify EK874 RZ/G2E board
  drivers: renesas: common: watchdog: Add support for RZ/G2E
  drivers: renesas: rzg: Add QoS support for RZ/G2E
  drivers: renesas: rzg: Add PFC support for RZ/G2E
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2N
  drivers: renesas: rzg: Add PFC support for RZ/G2N
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2H
  drivers: renesas: rzg: Add PFC support for RZ/G2H
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
  drivers: renesas: rzg: Switch using common ddr code
  drivers: renesas: ddr: Move to common
parents d8dc8c9e bcf43f04
Show whitespace changes
Inline Side-by-side
drivers/renesas/common/ddr/ddr.mk 0 → 100644
View file @ e9cd36f5
#
# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq ($(RCAR_LSI),$(filter $(RCAR_LSI),${RCAR_E3} ${RZ_G2E}))
include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
BL2_SOURCES += drivers/renesas/common/ddr/dram_sub_func.c
else ifeq (${RCAR_LSI},${RCAR_D3})
include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
else ifeq (${RCAR_LSI},${RCAR_V3M})
include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
else
include drivers/renesas/common/ddr/ddr_b/ddr_b.mk
BL2_SOURCES += drivers/renesas/common/ddr/dram_sub_func.c
endif
drivers/renesas/common/ddr/ddr_a/ddr_a.mk 0 → 100644
View file @ e9cd36f5
#
# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq ($(RCAR_LSI),$(filter $(RCAR_LSI),${RCAR_E3} ${RZ_G2E}))
BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
else ifeq (${RCAR_LSI},${RCAR_D3})
BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
else
BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
endif
drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c → drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
View file @ e9cd36f5
/* /*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. * Copyright (c) 2015-2021, Renesas Electronics Corporation.
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
...@@ -36,6 +36,10 @@ ...@@ -36,6 +36,10 @@
#define RCAR_E3 3 /* NON */ #define RCAR_E3 3 /* NON */
#define RCAR_H3N 4 #define RCAR_H3N 4
#define RZ_G2M 100U
#define RZ_G2H 101U
#define RZ_G2N 102U
#define RCAR_CUT_10 0 #define RCAR_CUT_10 0
#define RCAR_CUT_11 1 #define RCAR_CUT_11 1
#define RCAR_CUT_20 10 #define RCAR_CUT_20 10
...@@ -51,11 +55,11 @@ static uint32_t prr_cut; ...@@ -51,11 +55,11 @@ static uint32_t prr_cut;
#else #else
#if (RCAR_LSI == RCAR_H3) #if (RCAR_LSI == RCAR_H3)
static const uint32_t prr_product = PRR_PRODUCT_H3; static const uint32_t prr_product = PRR_PRODUCT_H3;
#elif(RCAR_LSI == RCAR_M3) #elif(RCAR_LSI == RCAR_M3 || RCAR_LSI == RZ_G2M)
static const uint32_t prr_product = PRR_PRODUCT_M3; static const uint32_t prr_product = PRR_PRODUCT_M3;
#elif(RCAR_LSI == RCAR_M3N) #elif(RCAR_LSI == RCAR_M3N || RCAR_LSI == RZ_G2N)
static const uint32_t prr_product = PRR_PRODUCT_M3N; static const uint32_t prr_product = PRR_PRODUCT_M3N;
#elif(RCAR_LSI == RCAR_H3N) #elif(RCAR_LSI == RCAR_H3N || RCAR_LSI == RZ_G2H)
static const uint32_t prr_product = PRR_PRODUCT_H3; static const uint32_t prr_product = PRR_PRODUCT_H3;
#endif /* RCAR_LSI */ #endif /* RCAR_LSI */
......
drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c → drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
View file @ e9cd36f5
/* /*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. * Copyright (c) 2015-2021, Renesas Electronics Corporation.
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef RZG_SOC
#define RZG_SOC 0
#endif
#if (RZG_SOC == 1)
#define BOARDNUM 4
#else
#define BOARDNUM 22 #define BOARDNUM 22
#endif /* RZG_SOC == 1 */
#define BOARD_JUDGE_AUTO #define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO #ifdef BOARD_JUDGE_AUTO
...@@ -66,6 +74,225 @@ struct _boardcnf { ...@@ -66,6 +74,225 @@ struct _boardcnf {
0x000F,\ 0x000F,\
0x010F} 0x010F}
#if (RZG_SOC == 1)
static const struct _boardcnf boardcnfs[BOARDNUM] = {
{
/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
.phyvalid = 0x03U,
.dbi_en = 0x01U,
.cacs_dly = 0x02c0U,
.cacs_dly_adj = 0x0U,
.dqdm_dly_w = 0x0300U,
.dqdm_dly_r = 0x00a0U,
.ch = {
{
{ 0x04U, 0xffU },
0x00345201UL,
0x3201U,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{
{ 0x04U, 0xffU },
0x00302154UL,
0x2310U,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
}
}
},
/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
{
0x03U,
0x01U,
0x02c0U,
0x0U,
0x0300U,
0x00a0U,
{
{
{ 0x02U, 0x02U },
0x00345201UL,
0x3201U,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{
{ 0x02U, 0x02U },
0x00302154UL,
0x2310,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
}
}
},
/* boardcnf[2] HopeRun HiHope RZ/G2H board 16Gbit/1rank/2ch */
{
0x05U,
0x01U,
0x0300U,
0,
0x0300U,
0x00a0U,
{
{
{ 0x04U, 0xffU },
0x00345201UL,
0x3201U,
{ 0x01672543U, 0x45367012U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{
{ 0x04U, 0xffU },
0x00302154UL,
0x2310U,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{
{ 0x04U, 0xffU },
0x00302154UL,
0x2310U,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{
{ 0xffU, 0xffU },
0UL,
0U,
{ 0U, 0U, 0U, 0U },
{ 0U, 0U, 0U, 0U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
}
}
},
/* boardcnf[3] HopeRun HiHope RZ/G2N board 16Gbit/2rank/1ch */
{
0x01U,
0x01U,
0x0300U,
0,
0x0300U,
0x00a0U,
{
{
{ 0x04U, 0x04U },
0x00345201UL,
0x3201U,
{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
{ 0x08U, 0x08U, 0x08U, 0x08U },
WDQLVL_PAT,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
}
}
},
};
#else
static const struct _boardcnf boardcnfs[BOARDNUM] = { static const struct _boardcnf boardcnfs[BOARDNUM] = {
{ {
/* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */ /* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */
...@@ -1535,6 +1762,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { ...@@ -1535,6 +1762,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
} }
} }
}; };
#endif /* RZG_SOC == 1 */
void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
{ {
...@@ -1636,7 +1864,7 @@ static const uint32_t termcode_by_sample[20][3] = { ...@@ -1636,7 +1864,7 @@ static const uint32_t termcode_by_sample[20][3] = {
#define GPIO_INDT5 0xE605500CU #define GPIO_INDT5 0xE605500CU
#define GPIO_GPSR6 0xE6060118U #define GPIO_GPSR6 0xE6060118U
#if (RCAR_GEN3_ULCB == 0) #if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0)
static void pfc_write_and_poll(uint32_t a, uint32_t v) static void pfc_write_and_poll(uint32_t a, uint32_t v)
{ {
mmio_write_32(PFC_PMMR, ~v); mmio_write_32(PFC_PMMR, ~v);
...@@ -1652,7 +1880,7 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v) ...@@ -1652,7 +1880,7 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v)
#define RCAR_GEN3_ULCB 0 #define RCAR_GEN3_ULCB 0
#endif #endif
#if (RCAR_GEN3_ULCB == 0) /* non Starter Kit */ #if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0) /* non Starter Kit */
static uint32_t opencheck_SSI_WS6(void) static uint32_t opencheck_SSI_WS6(void)
{ {
...@@ -1709,9 +1937,43 @@ static uint32_t opencheck_SSI_WS6(void) ...@@ -1709,9 +1937,43 @@ static uint32_t opencheck_SSI_WS6(void)
#endif #endif
#if (RZG_SOC == 1)
#define LPDDR4_2RANK (0x01U << 25U)
static uint32_t rzg2_board_judge(void)
{
uint32_t brd;
switch (prr_product) {
case PRR_PRODUCT_M3:
brd = 1U;
if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
if ((mmio_read_32(GPIO_INDT5) & LPDDR4_2RANK) == 0U) {
brd = 0U;
}
}
break;
case PRR_PRODUCT_H3:
brd = 2U;
break;
case PRR_PRODUCT_M3N:
brd = 3U;
break;
default:
brd = 99U;
}
return brd;
}
#endif /* RZG_SOC == 1 */
static uint32_t _board_judge(void) static uint32_t _board_judge(void)
{ {
uint32_t brd; uint32_t brd;
#if (RZG_SOC == 1)
brd = rzg2_board_judge();
#else
#if (RCAR_GEN3_ULCB == 1) #if (RCAR_GEN3_ULCB == 1)
/* Starter Kit */ /* Starter Kit */
if (prr_product == PRR_PRODUCT_H3) { if (prr_product == PRR_PRODUCT_H3) {
...@@ -1798,6 +2060,7 @@ static uint32_t _board_judge(void) ...@@ -1798,6 +2060,7 @@ static uint32_t _board_judge(void)
} }
} }
#endif #endif
#endif /* RZG_SOC == 1 */
return brd; return brd;
} }
......
drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk → drivers/renesas/common/ddr/ddr_b/ddr_b.mk
View file @ e9cd36f5
# #
# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. # Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
BL2_SOURCES += drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c BL2_SOURCES += drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
drivers/renesas/common/emmc/emmc_registers.h
View file @ e9cd36f5
...@@ -11,11 +11,11 @@ ...@@ -11,11 +11,11 @@
#define MMC_CH0 (0U) /* SDHI2/MMC0 */ #define MMC_CH0 (0U) /* SDHI2/MMC0 */
#define MMC_CH1 (1U) /* SDHI3/MMC1 */ #define MMC_CH1 (1U) /* SDHI3/MMC1 */
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2M) #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2M) || (RCAR_LSI == RZ_G2H) || (RCAR_LSI == RZ_G2N)
#define USE_MMC_CH (MMC_CH1) /* R-Car E3 or RZ/G2M */ #define USE_MMC_CH (MMC_CH1) /* R-Car E3 or RZ/G2{H,M,N} */
#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */ #else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */ #define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */ #endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
#define BIT0 (0x00000001U) #define BIT0 (0x00000001U)
#define BIT1 (0x00000002U) #define BIT1 (0x00000002U)
......
drivers/renesas/common/watchdog/swdt.c
View file @ e9cd36f5
...@@ -78,7 +78,7 @@ static void swdt_disable(void) ...@@ -78,7 +78,7 @@ static void swdt_disable(void)
void rcar_swdt_init(void) void rcar_swdt_init(void)
{ {
uint32_t rmsk, sr; uint32_t rmsk, sr;
#if (RCAR_LSI != RCAR_E3) #if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RZ_G2E)
uint32_t reg, val, product_cut, chk_data; uint32_t reg, val, product_cut, chk_data;
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
...@@ -94,7 +94,7 @@ void rcar_swdt_init(void) ...@@ -94,7 +94,7 @@ void rcar_swdt_init(void)
mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE | mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE |
WTCSRA_WOVFE | WTCSRA_CKS_DIV16); WTCSRA_WOVFE | WTCSRA_CKS_DIV16);
#if (RCAR_LSI == RCAR_E3) #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k); mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
#else #else
val = WTCNT_UPPER_BYTE; val = WTCNT_UPPER_BYTE;
......
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