Merge pull request #1660 from antonio-nino-diaz-arm/an/misra

Several MISRA defect fixes

plat/arm/board/fvp/include/platform_def.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 /* Enable the dynamic translation tables library. */
 #ifdef AARCH32
@@ -44,26 +44,26 @@
  */
 #define PLAT_ARM_CLUSTER_COUNT		FVP_CLUSTER_COUNT
 
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	UL(0x00040000)	/* 256 KB */
 
-#define PLAT_ARM_TRUSTED_ROM_BASE	0x00000000
-#define PLAT_ARM_TRUSTED_ROM_SIZE	0x04000000	/* 64 MB */
+#define PLAT_ARM_TRUSTED_ROM_BASE	UL(0x00000000)
+#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x04000000)	/* 64 MB */
 
-#define PLAT_ARM_TRUSTED_DRAM_BASE	0x06000000
-#define PLAT_ARM_TRUSTED_DRAM_SIZE	0x02000000	/* 32 MB */
+#define PLAT_ARM_TRUSTED_DRAM_BASE	UL(0x06000000)
+#define PLAT_ARM_TRUSTED_DRAM_SIZE	UL(0x02000000)	/* 32 MB */
 
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 
 /* No SCP in FVP */
-#define PLAT_ARM_SCP_TZC_DRAM1_SIZE	ULL(0x0)
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE	UL(0x0)
 
-#define PLAT_ARM_DRAM2_SIZE		ULL(0x80000000)
+#define PLAT_ARM_DRAM2_SIZE		UL(0x80000000)
 
 /*
  * Load address of BL33 for this platform port
  */
-#define PLAT_ARM_NS_IMAGE_OFFSET	(ARM_DRAM1_BASE + U(0x8000000))
+#define PLAT_ARM_NS_IMAGE_OFFSET	(ARM_DRAM1_BASE + UL(0x8000000))
 
 /*
  * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
@@ -94,18 +94,18 @@
  * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
  * plus a little space for growth.
  */
-#define PLAT_ARM_MAX_BL1_RW_SIZE	0xB000
+#define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0xB000)
 
 /*
  * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
  */
 
 #if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0x1000
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0xe000
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0xe000)
 #else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0)
 #endif
 
 /*
@@ -113,9 +113,9 @@
  * little space for growth.
  */
 #if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE		0x1D000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x1D000)
 #else
-# define PLAT_ARM_MAX_BL2_SIZE		0x11000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x11000)
 #endif
 
 /*
@@ -123,7 +123,7 @@
  * calculated using the current BL31 PROGBITS debug size plus the sizes of
  * BL2 and BL1-RW
  */
-#define PLAT_ARM_MAX_BL31_SIZE		0x3B000
+#define PLAT_ARM_MAX_BL31_SIZE		UL(0x3B000)
 
 #ifdef AARCH32
 /*
@@ -131,7 +131,7 @@
  * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
  * BL2 and BL1-RW
  */
-# define PLAT_ARM_MAX_BL32_SIZE		0x3B000
+# define PLAT_ARM_MAX_BL32_SIZE		UL(0x3B000)
 #endif
 
 /*
@@ -139,28 +139,28 @@
  */
 #if defined(IMAGE_BL1)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE 0x440
+#  define PLATFORM_STACK_SIZE		UL(0x440)
 # endif
 #elif defined(IMAGE_BL2)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE 0x400
+#  define PLATFORM_STACK_SIZE		UL(0x400)
 # endif
 #elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE		UL(0x400)
 #elif defined(IMAGE_BL31)
 # if ENABLE_SPM
-#  define PLATFORM_STACK_SIZE 0x500
+#  define PLATFORM_STACK_SIZE		UL(0x500)
 # elif PLAT_XLAT_TABLES_DYNAMIC
-#  define PLATFORM_STACK_SIZE 0x800
+#  define PLATFORM_STACK_SIZE		UL(0x800)
 # else
-#  define PLATFORM_STACK_SIZE 0x400
+#  define PLATFORM_STACK_SIZE		UL(0x400)
 # endif
 #elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
+# define PLATFORM_STACK_SIZE		UL(0x440)
 #endif
 
 #define MAX_IO_DEVICES			3
@@ -191,20 +191,20 @@
 #define PLAT_ARM_TSP_UART_BASE		V2M_IOFPGA_UART2_BASE
 #define PLAT_ARM_TSP_UART_CLK_IN_HZ	V2M_IOFPGA_UART2_CLK_IN_HZ
 
-#define PLAT_FVP_SMMUV3_BASE		0x2b400000
+#define PLAT_FVP_SMMUV3_BASE		UL(0x2b400000)
 
 /* CCI related constants */
-#define PLAT_FVP_CCI400_BASE		0x2c090000
+#define PLAT_FVP_CCI400_BASE		UL(0x2c090000)
 #define PLAT_FVP_CCI400_CLUS0_SL_PORT	3
 #define PLAT_FVP_CCI400_CLUS1_SL_PORT	4
 
 /* CCI-500/CCI-550 on Base platform */
-#define PLAT_FVP_CCI5XX_BASE		0x2a000000
+#define PLAT_FVP_CCI5XX_BASE		UL(0x2a000000)
 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT	5
 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT	6
 
 /* CCN related constants. Only CCN 502 is currently supported */
-#define PLAT_ARM_CCN_BASE		0x2e000000
+#define PLAT_ARM_CCN_BASE		UL(0x2e000000)
 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP	1, 5, 7, 11
 
 /* System timer related constants */
@@ -229,7 +229,7 @@
  * Give access to the CPUs and Virtio. Some devices
  * would normally use the default ID so allow that too.
  */
-#define PLAT_ARM_TZC_BASE		0x2a4a0000
+#define PLAT_ARM_TZC_BASE		UL(0x2a4a0000)
 #define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
 
 #define PLAT_ARM_TZC_NS_DEV_ACCESS	(				\
@@ -268,4 +268,4 @@
 #define PLAT_ARM_SP_IMAGE_STACK_BASE	(ARM_SP_IMAGE_NS_BUF_BASE +	\
 					 ARM_SP_IMAGE_NS_BUF_SIZE)
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/arm/board/juno/include/platform_def.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 /* Enable the dynamic translation tables library. */
 #ifdef AARCH32
@@ -41,7 +41,7 @@
 					JUNO_CLUSTER1_CORE_COUNT)
 
 /* Cryptocell HW Base address */
-#define PLAT_CRYPTOCELL_BASE		0x60050000
+#define PLAT_CRYPTOCELL_BASE		UL(0x60050000)
 
 /*
  * Other platform porting definitions are provided by included headers
@@ -52,13 +52,13 @@
  */
 #define PLAT_ARM_CLUSTER_COUNT		JUNO_CLUSTER_COUNT
 
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	UL(0x00040000)	/* 256 KB */
 
 /* Use the bypass address */
 #define PLAT_ARM_TRUSTED_ROM_BASE	V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
 
-#define NSRAM_BASE			0x2e000000
-#define NSRAM_SIZE			0x00008000	/* 32KB */
+#define NSRAM_BASE			UL(0x2e000000)
+#define NSRAM_SIZE			UL(0x00008000)	/* 32KB */
 
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
@@ -71,9 +71,9 @@
 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0
 
 #if TRUSTED_BOARD_BOOT
-#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00020000
+#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x00020000)
 #else
-#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00010000
+#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x00010000)
 #endif /* TRUSTED_BOARD_BOOT */
 
 /*
@@ -115,18 +115,18 @@
  * plus a little space for growth.
  */
 #if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL1_RW_SIZE	0xB000
+# define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0xB000)
 #else
-# define PLAT_ARM_MAX_BL1_RW_SIZE	0x6000
+# define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0x6000)
 #endif
 
 /*
  * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
  */
 #if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0x1000
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0x1000)
 #else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0)
 #endif
 
 /*
@@ -135,14 +135,14 @@
  */
 #if TRUSTED_BOARD_BOOT
 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
-# define PLAT_ARM_MAX_BL2_SIZE		0x1F000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x1F000)
 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA
-# define PLAT_ARM_MAX_BL2_SIZE		0x1D000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x1D000)
 #else
-# define PLAT_ARM_MAX_BL2_SIZE		0x1C000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x1C000)
 #endif
 #else
-# define PLAT_ARM_MAX_BL2_SIZE		0xF000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0xF000)
 #endif
 
 /*
@@ -151,7 +151,7 @@
  * BL2 and BL1-RW.  SCP_BL2 image is loaded into the space BL31 -> BL2_BASE.
  * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE.
  */
-#define PLAT_ARM_MAX_BL31_SIZE		0x3E000
+#define PLAT_ARM_MAX_BL31_SIZE		UL(0x3E000)
 
 #if JUNO_AARCH32_EL3_RUNTIME
 /*
@@ -160,7 +160,7 @@
  * BL2 and BL1-RW.  SCP_BL2 image is loaded into the space BL32 -> BL2_BASE.
  * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE.
  */
-#define PLAT_ARM_MAX_BL32_SIZE		0x3E000
+#define PLAT_ARM_MAX_BL32_SIZE		UL(0x3E000)
 #endif
 
 /*
@@ -168,26 +168,26 @@
  */
 #if defined(IMAGE_BL1)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE 0x440
+#  define PLATFORM_STACK_SIZE		UL(0x440)
 # endif
 #elif defined(IMAGE_BL2)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE 0x400
+#  define PLATFORM_STACK_SIZE		UL(0x400)
 # endif
 #elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE		UL(0x400)
 #elif defined(IMAGE_BL31)
 # if PLAT_XLAT_TABLES_DYNAMIC
-#  define PLATFORM_STACK_SIZE 0x800
+#  define PLATFORM_STACK_SIZE		UL(0x800)
 # else
-#  define PLATFORM_STACK_SIZE 0x400
+#  define PLATFORM_STACK_SIZE		UL(0x400)
 # endif
 #elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
+# define PLATFORM_STACK_SIZE		UL(0x440)
 #endif
 
 /*
@@ -197,7 +197,7 @@
 #define PLAT_LOG_LEVEL_ASSERT		40
 
 /* CCI related constants */
-#define PLAT_ARM_CCI_BASE		0x2c090000
+#define PLAT_ARM_CCI_BASE		UL(0x2c090000)
 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX	4
 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX	3
 
@@ -205,7 +205,7 @@
 #define PLAT_ARM_NSTIMER_FRAME_ID		1
 
 /* TZC related constants */
-#define PLAT_ARM_TZC_BASE		0x2a4a0000
+#define PLAT_ARM_TZC_BASE		UL(0x2a4a0000)
 #define PLAT_ARM_TZC_NS_DEV_ACCESS	(				\
 		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400)	|	\
 		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE)	|	\
@@ -223,13 +223,13 @@
  */
 
 /* GIC related constants (no GICR in GIC-400) */
-#define PLAT_ARM_GICD_BASE		0x2c010000
-#define PLAT_ARM_GICC_BASE		0x2c02f000
-#define PLAT_ARM_GICH_BASE		0x2c04f000
-#define PLAT_ARM_GICV_BASE		0x2c06f000
+#define PLAT_ARM_GICD_BASE		UL(0x2c010000)
+#define PLAT_ARM_GICC_BASE		UL(0x2c02f000)
+#define PLAT_ARM_GICH_BASE		UL(0x2c04f000)
+#define PLAT_ARM_GICV_BASE		UL(0x2c06f000)
 
 /* MHU related constants */
-#define PLAT_CSS_MHU_BASE		0x2b1f0000
+#define PLAT_CSS_MHU_BASE		UL(0x2b1f0000)
 
 /*
  * Base address of the first memory region used for communication between AP
@@ -243,7 +243,7 @@
  * 32-bit word on all CSS platforms. On Juno, part of this configuration is
  * which CPU is the primary, according to the shift and mask definitions below.
  */
-#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	(ARM_TRUSTED_SRAM_BASE + 0x80)
+#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	(ARM_TRUSTED_SRAM_BASE + UL(0x80))
 #define PLAT_CSS_PRIMARY_CPU_SHIFT		8
 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH		4
 #endif
@@ -252,13 +252,13 @@
  * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
  * SCP_BL2 size plus a little space for growth.
  */
-#define PLAT_CSS_MAX_SCP_BL2_SIZE	0x14000
+#define PLAT_CSS_MAX_SCP_BL2_SIZE	UL(0x14000)
 
 /*
  * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
  * SCP_BL2U size plus a little space for growth.
  */
-#define PLAT_CSS_MAX_SCP_BL2U_SIZE	0x14000
+#define PLAT_CSS_MAX_SCP_BL2U_SIZE	UL(0x14000)
 
 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
 	CSS_G1S_IRQ_PROPS(grp), \
@@ -287,9 +287,9 @@
  */
 
 /* CSS SoC NIC-400 Global Programmers View (GPV) */
-#define PLAT_SOC_CSS_NIC400_BASE	0x2a000000
+#define PLAT_SOC_CSS_NIC400_BASE	UL(0x2a000000)
 
 #define PLAT_ARM_PRIVATE_SDEI_EVENTS	ARM_SDEI_PRIVATE_EVENTS
 #define PLAT_ARM_SHARED_SDEI_EVENTS	ARM_SDEI_SHARED_EVENTS
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */

plat/arm/board/juno/juno_def.h

@@ -14,20 +14,20 @@
  ******************************************************************************/
 
 /* Board revisions */
-#define REV_JUNO_R0			0x1	/* Rev B */
-#define REV_JUNO_R1			0x2	/* Rev C */
-#define REV_JUNO_R2			0x3	/* Rev D */
+#define REV_JUNO_R0			U(0x1)	/* Rev B */
+#define REV_JUNO_R1			U(0x2)	/* Rev C */
+#define REV_JUNO_R2			U(0x3)	/* Rev D */
 
 /* Bypass offset from start of NOR flash */
-#define BL1_ROM_BYPASS_OFFSET		0x03EC0000
+#define BL1_ROM_BYPASS_OFFSET		UL(0x03EC0000)
 
-#define EMMC_BASE			0x0c000000
-#define EMMC_SIZE			0x04000000
+#define EMMC_BASE			UL(0x0c000000)
+#define EMMC_SIZE			UL(0x04000000)
 
-#define PSRAM_BASE			0x14000000
-#define PSRAM_SIZE			0x02000000
+#define PSRAM_BASE			UL(0x14000000)
+#define PSRAM_SIZE			UL(0x02000000)
 
-#define JUNO_SSC_VER_PART_NUM		0x030
+#define JUNO_SSC_VER_PART_NUM		U(0x030)
 
 /*******************************************************************************
  * Juno topology related constants
@@ -54,19 +54,19 @@
 /*******************************************************************************
  * TRNG related constants
  ******************************************************************************/
-#define TRNG_BASE	0x7FE60000ULL
+#define TRNG_BASE	UL(0x7FE60000)
 #define TRNG_NOUTPUTS	4
-#define TRNG_STATUS	0x10
-#define TRNG_INTMASK	0x14
-#define TRNG_CONFIG	0x18
-#define TRNG_CONTROL	0x1C
+#define TRNG_STATUS	UL(0x10)
+#define TRNG_INTMASK	UL(0x14)
+#define TRNG_CONFIG	UL(0x18)
+#define TRNG_CONTROL	UL(0x1C)
 #define TRNG_NBYTES	16	/* Number of bytes generated per round. */
 
 /*******************************************************************************
  * MMU-401 related constants
  ******************************************************************************/
-#define MMU401_SSD_OFFSET		0x4000
-#define MMU401_DMA330_BASE		0x7fb00000
+#define MMU401_SSD_OFFSET		UL(0x4000)
+#define MMU401_DMA330_BASE		UL(0x7fb00000)
 
 /*******************************************************************************
  * Interrupt handling constants

plat/arm/common/arm_common.c

@@ -63,7 +63,7 @@ uint32_t arm_get_spsr_for_bl33_entry(void)
 	uint32_t spsr;
 
 	/* Figure out what mode we enter the non-secure world in */
-	mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+	mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
 
 	/*
 	 * TODO: Consider the possibility of specifying the SPSR in

plat/arm/common/arm_dyn_cfg.c

@@ -122,8 +122,8 @@ void arm_bl1_set_mbedtls_heap(void)
 void arm_load_tb_fw_config(void)
 {
 	int err;
-	uintptr_t config_base = 0;
-	image_desc_t *image_desc;
+	uintptr_t config_base = 0UL;
+	image_desc_t *desc;
 
 	image_desc_t arm_tb_fw_info = {
 		.image_id = TB_FW_CONFIG_ID,
@@ -148,12 +148,11 @@ void arm_load_tb_fw_config(void)
 	tb_fw_cfg_dtb_size = (size_t)arm_tb_fw_info.image_info.image_max_size;
 
 	/* The BL2 ep_info arg0 is modified to point to TB_FW_CONFIG */
-	image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
-	assert(image_desc != NULL);
-	image_desc->ep_info.args.arg0 = config_base;
+	desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
+	assert(desc != NULL);
+	desc->ep_info.args.arg0 = config_base;
 
-	INFO("BL1: TB_FW_CONFIG loaded at address = %p\n",
-			(void *) config_base);
+	INFO("BL1: TB_FW_CONFIG loaded at address = 0x%lx\n", config_base);
 
 #if TRUSTED_BOARD_BOOT && defined(DYN_DISABLE_AUTH)
 	int tb_fw_node;
@@ -240,7 +239,7 @@ void arm_bl2_dyn_cfg_init(void)
 		 */
 		if (config_ids[i] != HW_CONFIG_ID) {
 
-			if (check_uptr_overflow(image_base, image_size) != 0)
+			if (check_uptr_overflow(image_base, image_size))
 				continue;
 
 			/* Ensure the configs don't overlap with BL31 */

plat/arm/common/execution_state_switch.c

@@ -117,7 +117,7 @@ int arm_execution_state_switch(unsigned int smc_fid,
 		 * Switching from AArch64 to AArch32. Ensure this CPU implements
 		 * the target EL in AArch32.
 		 */
-		impl = from_el2 ? EL_IMPLEMENTED(2) : EL_IMPLEMENTED(1);
+		impl = from_el2 ? el_implemented(2) : el_implemented(1);
 		if (impl != EL_IMPL_A64_A32)
 			goto exec_denied;
 

plat/hisilicon/hikey/hikey_bl2_setup.c

@@ -99,7 +99,7 @@ uint32_t hikey_get_spsr_for_bl33_entry(void)
 	uint32_t spsr;
 
 	/* Figure out what mode we enter the non-secure world in */
-	mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+	mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
 
 	/*
 	 * TODO: Consider the possibility of specifying the SPSR in

plat/hisilicon/hikey960/hikey960_bl2_setup.c

@@ -191,7 +191,7 @@ uint32_t hikey960_get_spsr_for_bl33_entry(void)
 	uint32_t spsr;
 
 	/* Figure out what mode we enter the non-secure world in */
-	mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+	mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
 
 	/*
 	 * TODO: Consider the possibility of specifying the SPSR in

plat/layerscape/common/ls_common.c

@@ -147,7 +147,7 @@ uint32_t ls_get_spsr_for_bl33_entry(void)
 	uint32_t spsr;
 
 	/* Figure out what mode we enter the non-secure world in */
-	mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+	mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
 
 	/*
 	 * TODO: Consider the possibility of specifying the SPSR in

plat/mediatek/mt6795/bl31_plat_setup.c

@@ -339,7 +339,7 @@ static entry_point_info_t *bl31_plat_get_next_kernel64_ep_info(void)
 	next_image_info = &bl33_image_ep_info;
 
 	/* Figure out what mode we enter the non-secure world in */
-	if (EL_IMPLEMENTED(2)) {
+	if (el_implemented(2) != EL_IMPL_NONE) {
 		INFO("Kernel_EL2\n");
 		mode = MODE_EL2;
 	} else{

plat/qemu/qemu_bl2_setup.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -118,7 +118,7 @@ static uint32_t qemu_get_spsr_for_bl33_entry(void)
 	unsigned int mode;
 
 	/* Figure out what mode we enter the non-secure world in */
-	mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+	mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
 
 	/*
 	 * TODO: Consider the possibility of specifying the SPSR in