Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09

Marvell updates 18.09

docs/marvell/build.txt

@@ -22,14 +22,14 @@ Build Instructions
 
 	   u-boot.bin should be used and not u-boot-spl.bin
 
-	Set MSS/SCP image path (mandatory only for Armada80x0 and Aramada8xxy)::
+	Set MSS/SCP image path (mandatory only for Armada80x0)::
 
 		> export SCP_BL2=path/to/mrvl_scp_bl2*.img
 
 (3) Armada-37x0 build requires WTP tools installation.
 
-	See below in the section "Tools Installation for Armada37x0 Builds".
-	Install ARM 32-bit cross compiler, which is required by building WTMI image for CM3::
+	See below in the section "Tools and external components installation".
+	Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3::
 
 		> sudo apt-get install gcc-arm-linux-gnueabi
 
@@ -42,6 +42,8 @@ Build Instructions
 	There are several build options:
 
 	- DEBUG: default is without debug information (=0). in order to enable it use DEBUG=1
+		Must be disabled when building UART recovery images due to current console driver
+		implementation that is not compatible with Xmodem protocol used for boot image download.
 
 	- LOG_LEVEL: defines the level of logging which will be purged to the default output port.
 
@@ -55,13 +57,14 @@ Build Instructions
 	- USE_COHERENT_MEM: This flag determines whether to include the coherent memory region in the
 		BL memory map or not.
 
-	-LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1).
+	- LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1).
 
 	- MARVELL_SECURE_BOOT: build trusted(=1)/non trusted(=0) image, default is non trusted.
 
 	- BLE_PATH:
-		Points to BLE (Binary ROM extension) sources folder. Only required for A8K and A8K+ builds.
+		Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds.
 		The parameter is optional, its default value is "ble".
+		For the BLE source location, check the section "Tools and external components installation"
 
 	- MV_DDR_PATH:
 		For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
@@ -70,6 +73,7 @@ Build Instructions
 		The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr
 		sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
 		is necessary for A37x0.
+		For the mv_ddr source location, check the section "Tools and external components installation"
 
 	- DDR_TOPOLOGY: For Armada37x0 only, the DDR topology map index/name, default is 0.
 		Supported Options:
@@ -106,45 +110,35 @@ Build Instructions
 		nothing, an image which supports EFUSE or a customized CM3 firmware binary. The default image
 		is wtmi.bin that built from sources in WTP folder, which is the next option. If the default
 		image is OK, then this option should be skipped.
+
 	- WTP: For Armada37x0 only, use this parameter to point to wtptools source code directory, which
 		can be found as a3700_utils.zip in the release.
 		Usage example: WTP=/path/to/a3700_utils
 
-	- CP_NUM: Total amount of CPs (South Bridge) chips wired to the interconnected APs.
-		When the parameter is omitted, the build is uses the default number of CPs equal to 2.
-		The parameter is valid for Armada 8K-plus SoC family (PLAT=a8xxy) and results in a build of images
-		suitable for a8xxY SoC, where "Y" is a number of connected CPs and "xx" is a number of CPU cores.
-		Valid values with CP_NUM is in a range of 0 to 8.
-		The CPs defined by this parameter are evenly distributed across interconnected APs that in turn
-		are dynamically detected. For instance, if the CP_NUM=6 and the TF-A detects 2 interconnected
-		APs, each AP assumed to have 3 attached CPs. With the same amount of APs and CP_NUM=3, the AP0
-		will have 2 CPs connected and AP1 - a just single CP.
-
 	For example, in order to build the image in debug mode with log level up to 'notice' level run::
 
 		> make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> all fip
 
 	And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level,
-	the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR3 2CS,
+	the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
 	the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
 	line is as following::
 
 		> make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 SECURE=0 CLOCKSPRESET=CPU_1000_DDR_800 \
-			DDR_TOPOLOGY=2 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip
+			DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip
 
 	Supported MARVELL_PLATFORM are:
-		- a3700
+		- a3700 (for both A3720 DB and EspressoBin)
 		- a70x0
 		- a70x0_amc (for AMC board)
-		- a70x0_cust (for customers)
 		- a80x0
 		- a80x0_mcbin (for MacciatoBin)
 
 Special Build Flags
 --------------------
 	- PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build
-		atf. In order to build uart recovery image this operation should be disabled for a70x0 and a80x0
-                because of hardware limitation(boot from secondary image can interrupt uart recovery process).
+		atf. In order to build UART recovery image this operation should be disabled for a70x0 and a80x0
+                because of hardware limitation (boot from secondary image can interrupt UART recovery process).
 		This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file
 
 (for more information about build options, please refer to section 'Summary of build options' in  TF-A user-guide:
@@ -160,22 +154,44 @@ Marvell's TF-A compilation generates 7 files:
 	- bl31.bin		- BL31 image
 	- fip.bin		- FIP image (contains BL2, BL31 & BL33 (U-Boot) images)
 	- boot-image.bin	- TF-A image (contains BL1 and FIP images)
-	- flash-image.bin	- Image which contains boot-image.bin and SPL image; should be placed on the boot flash/device.
+	- flash-image.bin	- Image which contains boot-image.bin and SPL image;
+				  should be placed on the boot flash/device.
+
 
+Tools and external components installation
+==========================================
 
-Tools Installation for Armada37x0 Builds
------------------------------------------
-Install a cross GNU ARM tool chain for building the WTMI binary.
-Any cross GNU ARM tool chain that is able to build ARM Cortex M3 binaries
-is suitable.
+Armada37x0 Builds require installation of 3 components
+-------------------------------------------------------
 
-On Debian/Uboot hosts the default GNU ARM tool chain can be installed
-using the following command::
+(1) ARM cross compiler capable of building images for the service CPU (CM3).
+    This component is usually included in the Linux host packages.
+    On Debian/Uboot hosts the default GNU ARM tool chain can be installed
+    using the following command::
 
 		> sudo apt-get install gcc-arm-linux-gnueabi
 
-If required, the default tool chain prefix "arm-linux-gnueabi-" can be
-overwritten using the environment variable CROSS_CM3.
-Example for BASH shell::
+    Only if required, the default tool chain prefix "arm-linux-gnueabi-" can be
+    overwritten using the environment variable CROSS_CM3.
+    Example for BASH shell::
 
 		> export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi
+
+(2) DDR initialization library sources (mv_ddr) available at the following repository
+    (use the "mv_ddr-armada-atf-mainline" branch)::
+    https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
+
+(3) Armada3700 tools available at the following repository (use the latest release branch)::
+    https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
+
+Armada70x0 and Armada80x0 Builds require installation of 2 components
+---------------------------------------------------------------------
+
+(1) DDR initialization library sources (mv_ddr) available at the following repository
+    (use the "mv_ddr-armada-atf-mainline" branch)::
+    https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
+
+(2) BLE sources available at the following repository (use the "atf-mainline" branch)::
+    https://github.com/MarvellEmbeddedProcessors/ble-marvell.git
+
+

drivers/arm/gic/v2/gicv2_main.c

@@ -597,3 +597,12 @@ unsigned int gicv2_set_pmr(unsigned int mask)
 
 	return old_mask;
 }
+
+/*******************************************************************************
+ * This function updates single interrupt configuration to be level/edge
+ * triggered
+ ******************************************************************************/
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg)
+{
+	gicd_set_icfgr(driver_data->gicd_base, id, cfg);
+}

drivers/marvell/amb_adec.c

@@ -7,7 +7,7 @@
 
 /* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */
 
-#include <a8k_common.h>
+#include <armada_common.h>
 #include <debug.h>
 #include <mmio.h>
 #include <mvebu.h>

drivers/marvell/ccu.c

@@ -7,7 +7,7 @@
 
 /* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
 
-#include <a8k_common.h>
+#include <armada_common.h>
 #include <ccu.h>
 #include <debug.h>
 #include <mmio.h>

drivers/marvell/comphy/comphy-cp110.h

@@ -217,9 +217,9 @@
 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET	0
 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK	\
 			(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET	3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK	\
-			(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET	3
+#define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK	\
+			(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET)
 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET	6
 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK	\
 			(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
@@ -251,9 +251,9 @@
 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET	0
 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK	\
 			(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET	3
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK	\
-			(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET	3
+#define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK	\
+			(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET)
 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET	6
 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK	\
 			(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)

drivers/marvell/comphy/phy-comphy-cp110.c

@@ -481,8 +481,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
 	/* G1 settings */
 	mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
 	data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-	mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+	mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
 	data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
@@ -506,8 +506,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
 	/* G2 settings */
 	mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
 	data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
-	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
-	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
+	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
 	data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
@@ -1000,13 +1000,13 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
 	if (speed == COMPHY_SPEED_5_15625G) {
 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
 		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
 	} else {
 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
 		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
 		data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
@@ -1504,8 +1504,8 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base,
 	/* Genration 2 setting 1*/
 	mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
 	data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
-	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
-	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
+	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
 	data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
@@ -1741,8 +1741,8 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base,
 	/* 0xE-G1_Setting_1 */
 	mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
 	data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
-	mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+	mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
+	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
 	mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
@@ -2201,7 +2201,7 @@ int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base,
 	return 0;
 }
 
-int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index,
+int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
 				uint64_t comphy_mode)
 {
 	int mode = COMPHY_GET_MODE(comphy_mode);
@@ -2247,7 +2247,7 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index,
 		err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index);
 		break;
 	default:
-		ERROR("comphy%lld: unsupported comphy mode\n", comphy_index);
+		ERROR("comphy%d: unsupported comphy mode\n", comphy_index);
 		err = -EINVAL;
 		break;
 	}
@@ -2257,7 +2257,7 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index,
 	return err;
 }
 
-int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint64_t comphy_index)
+int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint8_t comphy_index)
 {
 	uintptr_t sd_ip_addr, comphy_ip_addr;
 	uint32_t mask, data;

drivers/marvell/comphy/phy-comphy-cp110.h

@@ -8,11 +8,11 @@
 /* Marvell CP110 SoC COMPHY unit driver */
 
 int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
-				     uint64_t comphy_index);
+				     uint8_t comphy_index);
 int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
-				 uint64_t comphy_index);
+				 uint8_t comphy_index);
 int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
-				uint64_t comphy_index, uint64_t comphy_mode);
+				uint8_t comphy_index, uint64_t comphy_mode);
 int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
 				       uint8_t comphy_index);
 int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,

drivers/marvell/gwin.c

@@ -7,7 +7,7 @@
 
 /* GWIN unit device driver for Marvell AP810 SoC */
 
-#include <a8k_common.h>
+#include <armada_common.h>
 #include <debug.h>
 #include <gwin.h>
 #include <mmio.h>

drivers/marvell/i2c/a8k_i2c.c

@@ -442,7 +442,7 @@ static int marvell_i2c_unstuck(int ret)
 void i2c_init(void *i2c_base)
 {
 	/* For I2C speed and slave address, now we do not set them since
-	 * we just provide the working speed and slave address in plat_def.h
+	 * we just provide the working speed and slave address in mvebu_def.h
 	 * for i2c_init
 	 */
 	base = (struct marvell_i2c_regs *)i2c_base;

drivers/marvell/io_win.c

@@ -7,7 +7,7 @@
 
 /* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */
 
-#include <a8k_common.h>
+#include <armada_common.h>
 #include <debug.h>
 #include <io_win.h>
 #include <mmio.h>

drivers/marvell/iob.c

@@ -7,7 +7,7 @@
 
 /* IOW unit device driver for Marvell CP110 and CP115 SoCs */
 
-#include <a8k_common.h>
+#include <armada_common.h>
 #include <arch_helpers.h>
 #include <debug.h>
 #include <iob.h>

drivers/marvell/mc_trustzone/mc_trustzone.c

+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <addr_map.h>
+#include <debug.h>
+#include <mmio.h>
+#include <mvebu_def.h>
+#include "mc_trustzone.h"
+
+#define TZ_SIZE(x)		((x) >> 13)
+
+static int fls(int x)
+{
+	if (!x)
+		return 0;
+
+	return 32 - __builtin_clz(x);
+}
+
+/* To not duplicate types, the addr_map_win is used, but the "target"
+ * filed is referring to attributes instead of "target".
+ */
+void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id)
+{
+	int tz_size;
+	uint32_t val, base = win->base_addr;
+
+	if ((win_id < 0) || (win_id > MVEBU_TZ_MAX_WINS)) {
+		ERROR("Enabling wrong MC TrustZone window %d!\n", win_id);
+		return;
+	}
+
+	/* map the window size to trustzone register convention */
+	tz_size = fls(TZ_SIZE(win->win_size));
+
+	VERBOSE("%s: window size = 0x%llx maps to tz_size %d\n",
+		__func__, win->win_size, tz_size);
+	if (tz_size < 0 || tz_size > 31) {
+		ERROR("Using not allowed size for MC TrustZone window %d!\n",
+		      win_id);
+		return;
+	}
+
+	if (base & 0xfff) {
+		base = base & ~0xfff;
+		WARN("Attempt to open MC TZ win. at 0x%llx, truncate to 0x%x\n",
+		     win->base_addr, base);
+	}
+
+	val = base | (tz_size << 7) | win->target_id | TZ_VALID;
+
+	VERBOSE("%s: base 0x%x, tz_size moved 0x%x, attr 0x%x, val 0x%x\n",
+		__func__, base, (tz_size << 7), win->target_id, val);
+
+	mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), val);
+
+	VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id,
+		MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id),
+		mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id)));
+
+	mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id),
+		     (win->base_addr >> 32));
+
+	VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id,
+		MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id),
+		mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id)));
+}

drivers/marvell/mc_trustzone/mc_trustzone.h

+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef _MC_TRUSTZONE_H
+#define _MC_TRUSTZONE_H
+
+#include <addr_map.h>
+
+#define MVEBU_TZ_MAX_WINS	16
+
+#define TZ_VALID		(1 << 0)
+#define TZ_PERM(x)		((x) << 1)
+#define TZ_RZ_ENABLE		(1 << 3)
+
+/* tz attr definitions */
+#define TZ_PERM_RW		(TZ_PERM(0))
+#define TZ_PERM_RO		(TZ_PERM(1))
+#define TZ_PERM_WO		(TZ_PERM(2))
+#define TZ_PERM_ABORT		(TZ_PERM(3))
+
+void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id);
+
+#endif /* _MC_TRUSTZONE_H */

drivers/marvell/mochi/cp110_setup.c

@@ -341,10 +341,6 @@ static void cp110_rtc_init(uintptr_t base)
 		mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0);
 		mdelay(500);
 
-		/* Reset Time register */
-		mmio_write_32(base + MVEBU_RTC_TIME_REG, 0);
-		udelay(62);
-
 		/* Reset Status register */
 		mmio_write_32(base + MVEBU_RTC_STATUS_REG,
 			      (MVEBU_RTC_STATUS_ALARM1_MASK |
@@ -361,10 +357,6 @@ static void cp110_rtc_init(uintptr_t base)
 		mmio_write_32(base + MVEBU_RTC_CCR_REG,
 			      MVEBU_RTC_NOMINAL_TIMING);
 
-		/* Reset Time register */
-		mmio_write_32(base + MVEBU_RTC_TIME_REG, 0);
-		udelay(10);
-
 		/* Reset Status register */
 		mmio_write_32(base + MVEBU_RTC_STATUS_REG,
 			      (MVEBU_RTC_STATUS_ALARM1_MASK |

include/drivers/arm/gicv2.h

@@ -191,6 +191,7 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num);
 void gicv2_set_interrupt_pending(unsigned int id);
 void gicv2_clear_interrupt_pending(unsigned int id);
 unsigned int gicv2_set_pmr(unsigned int mask);
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __GICV2_H__ */

include/drivers/marvell/aro.h

@@ -29,6 +29,7 @@ enum cpu_clock_freq_mode {
 	CPU_1800_DDR_1050_RCLK_1050 = 0x7,
 	CPU_1600_DDR_900_RCLK_900   = 0x0B,
 	CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
+	CPU_1600_DDR_1200_RCLK_1200 = 0x0D,
 	CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
 	CPU_1000_DDR_650_RCLK_650   = 0x13,
 	CPU_1300_DDR_800_RCLK_800   = 0x14,

include/drivers/marvell/mochi/cp110_setup.h

@@ -20,6 +20,7 @@
 #define MVEBU_DEVICE_REV_MASK		(0xf << MVEBU_DEVICE_REV_OFFSET)
 #define MVEBU_70X0_DEV_ID		(0x7040)
 #define MVEBU_70X0_CP115_DEV_ID		(0x7045)
+#define MVEBU_3900_DEV_ID		(0x6025)
 #define MVEBU_80X0_DEV_ID		(0x8040)
 #define MVEBU_80X0_CP115_DEV_ID		(0x8045)
 #define MVEBU_CP110_SA_DEV_ID		(0x110)

include/plat/marvell/a8k/common/marvell_def.h

@@ -63,6 +63,7 @@
 #define MARVELL_DRAM_END		(MARVELL_DRAM_BASE + \
 					 MARVELL_DRAM_SIZE - 1)
 
+#define MARVELL_IRQ_PIC0		28
 #define MARVELL_IRQ_SEC_PHY_TIMER	29
 
 #define MARVELL_IRQ_SEC_SGI_0		8

include/plat/marvell/a8k/common/plat_marvell.h

@@ -93,6 +93,14 @@ int marvell_io_is_toc_valid(void);
 void marvell_psci_arch_init(int ap_idx);
 void plat_marvell_system_reset(void);
 
+/*
+ * Miscellaneous platform SMC routines
+ */
+#ifdef MVEBU_PMU_IRQ_WA
+void mvebu_pmu_interrupt_enable(void);
+void mvebu_pmu_interrupt_disable(void);
+#endif
+
 /*
  * Optional functions required in Marvell standard platforms
  */