diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 2e7476a17fcdb9bb62bba65af28674db79d0fdd9..e4dfea434c2c0da60ecc7a6c58b5513f55480ccf 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -72,11 +72,13 @@ func bl31_entrypoint
isb
/* ---------------------------------------------
- * Set the exception vector to something sane.
+ * Set the exception vector and zero tpidr_el3
+ * until the crash reporting is set up
* ---------------------------------------------
*/
- adr x1, early_exceptions
+ adr x1, runtime_exceptions
msr vbar_el3, x1
+ msr tpidr_el3, xzr
/* ---------------------------------------------------------------------
* The initial state of the Architectural feature trap register
@@ -134,10 +136,10 @@ func bl31_entrypoint
* Initialise cpu_data and crash reporting
* ---------------------------------------------
*/
- bl init_cpu_data_ptr
#if CRASH_REPORTING
bl init_crash_reporting
#endif
+ bl init_cpu_data_ptr
/* ---------------------------------------------
* Use SP_EL0 for the C runtime stack.
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 4602e4113900d64c218ee760f572ebf48104cae8..5555c319c3b68a01072db0f79dbf36b946727859 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -38,8 +38,7 @@ BL31_SOURCES += bl31/bl31_main.c \
bl31/aarch64/context.S \
bl31/aarch64/cpu_data.S \
bl31/aarch64/runtime_exceptions.S \
- bl31/aarch64/crash_reporting.S \
- common/aarch64/early_exceptions.S \
+ bl31/aarch64/crash_reporting.S \
lib/aarch64/cpu_helpers.S \
lib/locks/bakery/bakery_lock.c \
lib/locks/exclusive/spinlock.S \
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 5bb11ba3cf7318f2db68d3f715a8cb9cbd4c84f4..6f88e65629f706228098dd1c03671f0ffcfa39b0 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -71,7 +71,6 @@ void bl31_lib_init()
******************************************************************************/
void bl31_main(void)
{
-
/* Perform remaining generic architectural setup from EL3 */
bl31_arch_setup();
@@ -89,16 +88,7 @@ void bl31_main(void)
/* Clean caches before re-entering normal world */
dcsw_op_all(DCCSW);
- /*
- * Use the more complex exception vectors now that context
- * management is setup. SP_EL3 should point to a 'cpu_context'
- * structure which has an exception stack allocated. The PSCI
- * service should have set the context.
- */
- assert(cm_get_context(NON_SECURE));
- cm_set_next_eret_context(NON_SECURE);
- write_vbar_el3((uint64_t) runtime_exceptions);
- isb();
+ /* By default run the non-secure BL3-3 image next */
next_image_type = NON_SECURE;
/*
diff --git a/include/bl31/runtime_svc.h b/include/bl31/runtime_svc.h
index 3b84f060cad04f7ec0cb8ff1497e7c6917900ae6..f3543d4f9fb1ab0c6cbde1b5e46fb1e72c7cec72 100644
--- a/include/bl31/runtime_svc.h
+++ b/include/bl31/runtime_svc.h
@@ -268,7 +268,6 @@ void runtime_svc_init();
extern uint64_t __RT_SVC_DESCS_START__;
extern uint64_t __RT_SVC_DESCS_END__;
void init_crash_reporting(void);
-void runtime_exceptions(void);
#endif /*__ASSEMBLY__*/
#endif /* __RUNTIME_SVC_H__ */
diff --git a/services/std_svc/psci/psci_afflvl_on.c b/services/std_svc/psci/psci_afflvl_on.c
index 1c7a87725d40bf41c3110e768533eb452f18b9da..e4d8f1f2a3208a09b54246e189be50ca1d0fe285 100644
--- a/services/std_svc/psci/psci_afflvl_on.c
+++ b/services/std_svc/psci/psci_afflvl_on.c
@@ -372,16 +372,6 @@ static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
*/
bl31_arch_setup();
- /*
- * Use the more complex exception vectors to enable SPD
- * initialisation. SP_EL3 should point to a 'cpu_context'
- * structure. The calling cpu should have set the
- * context already
- */
- assert(cm_get_context(NON_SECURE));
- cm_set_next_eret_context(NON_SECURE);
- write_vbar_el3((uint64_t) runtime_exceptions);
-
/*
* Call the cpu on finish handler registered by the Secure Payload
* Dispatcher to let it do any bookeeping. If the handler encounters an
diff --git a/services/std_svc/psci/psci_afflvl_suspend.c b/services/std_svc/psci/psci_afflvl_suspend.c
index 3a1a419a9c5ab35f65b90190e462a46b6cc2787f..993431048d3c6a10bc63183fe2b08c890c48c81d 100644
--- a/services/std_svc/psci/psci_afflvl_suspend.c
+++ b/services/std_svc/psci/psci_afflvl_suspend.c
@@ -490,15 +490,6 @@ static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr,
cm_el3_sysregs_context_restore(NON_SECURE);
rc = PSCI_E_SUCCESS;
- /*
- * Use the more complex exception vectors to enable SPD
- * initialisation. SP_EL3 should point to a 'cpu_context'
- * structure. The non-secure context should have been
- * set on this cpu prior to suspension.
- */
- cm_set_next_eret_context(NON_SECURE);
- write_vbar_el3((uint64_t) runtime_exceptions);
-
/*
* Call the cpu suspend finish handler registered by the Secure Payload
* Dispatcher to let it do any bookeeping. If the handler encounters an
diff --git a/services/std_svc/psci/psci_entry.S b/services/std_svc/psci/psci_entry.S
index 037673ddb1fb05fd3f1582bd3b460febcb3fda6c..5628d79178331cbb9c245b338ff156eca14bed98 100644
--- a/services/std_svc/psci/psci_entry.S
+++ b/services/std_svc/psci/psci_entry.S
@@ -67,12 +67,10 @@ psci_aff_common_finish_entry:
bl init_cpu_data_ptr
/* ---------------------------------------------
- * Exceptions should not occur at this point.
- * Set VBAR in order to handle and report any
- * that do occur
+ * Set the exception vectors
* ---------------------------------------------
*/
- adr x0, early_exceptions
+ adr x0, runtime_exceptions
msr vbar_el3, x0
isb