plat/css: allow platforms to define the system power domain level

The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain
level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the
system power domain level can be different for CSS platforms that
use multi-threaded CPUs.

So, in preparation towards adding support for platforms that use
multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL
such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the
CSS platform.

Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

include/plat/arm/css/common/css_pm.h

@@ -11,9 +11,6 @@
 #include <psci.h>
 #include <stdint.h>
 
-/* System power domain at level 2, as currently implemented by CSS platforms */
-#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
-
 /* Macros to read the CSS power domain state */
 #define CSS_CORE_PWR_STATE(state)	(state)->pwr_domain_state[ARM_PWR_LVL0]
 #define CSS_CLUSTER_PWR_STATE(state)	(state)->pwr_domain_state[ARM_PWR_LVL1]

plat/arm/board/juno/include/platform_def.h

@@ -292,4 +292,7 @@
 #define PLAT_ARM_PRIVATE_SDEI_EVENTS	ARM_SDEI_PRIVATE_EVENTS
 #define PLAT_ARM_SHARED_SDEI_EVENTS	ARM_SDEI_SHARED_EVENTS
 
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
+
 #endif /* PLATFORM_DEF_H */

plat/arm/board/n1sdp/include/platform_def.h

@@ -32,6 +32,8 @@
 						N1SDP_MAX_CPUS_PER_CLUSTER *	\
 						N1SDP_MAX_PE_PER_CPU)
 
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL			ARM_PWR_LVL2
 
 /*
  * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the

plat/arm/board/sgi575/include/platform_def.h

@@ -20,4 +20,7 @@
 #define SGI575_DMC620_BASE0		UL(0x4e000000)
 #define SGI575_DMC620_BASE1		UL(0x4e100000)
 
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
+
 #endif /* PLATFORM_DEF_H */

plat/arm/board/sgiclarka/include/platform_def.h

@@ -20,4 +20,7 @@
 #define SGICLARKA_DMC620_BASE0		UL(0x4e000000)
 #define SGICLARKA_DMC620_BASE1		UL(0x4e100000)
 
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
+
 #endif /* PLATFORM_DEF_H */

plat/arm/css/sgm/include/sgm_base_platform_def.h

@@ -239,4 +239,8 @@
  */
 #define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE + \
 					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
+
 #endif /* SGM_BASE_PLATFORM_DEF_H */