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adam.huang
Arm Trusted Firmware
Commits
effe0dca
Commit
effe0dca
authored
Mar 17, 2017
by
davidcunado-arm
Committed by
GitHub
Mar 17, 2017
Browse files
Merge pull request #858 from soby-mathew/sm/gic_driver_data_fix
Flush the GIC driver data after init
parents
510a9de7
311b1773
Changes
2
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drivers/arm/gic/v2/gicv2_main.c
View file @
effe0dca
/*
/*
* Copyright (c) 2015-201
6
, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-201
7
, ARM Limited and Contributors. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* modification, are permitted provided that the following conditions are met:
...
@@ -158,6 +158,17 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
...
@@ -158,6 +158,17 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
driver_data
=
plat_driver_data
;
driver_data
=
plat_driver_data
;
/*
* The GIC driver data is initialized by the primary CPU with caches
* enabled. When the secondary CPU boots up, it initializes the
* GICC/GICR interface with the caches disabled. Hence flush the
* driver_data to ensure coherency. This is not required if the
* platform has HW_ASSISTED_COHERENCY enabled.
*/
#if !HW_ASSISTED_COHERENCY
flush_dcache_range
((
uintptr_t
)
&
driver_data
,
sizeof
(
driver_data
));
flush_dcache_range
((
uintptr_t
)
driver_data
,
sizeof
(
*
driver_data
));
#endif
INFO
(
"ARM GICv2 driver initialized
\n
"
);
INFO
(
"ARM GICv2 driver initialized
\n
"
);
}
}
...
...
drivers/arm/gic/v3/gicv3_main.c
View file @
effe0dca
/*
/*
* Copyright (c) 2015-201
6
, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-201
7
, ARM Limited and Contributors. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* modification, are permitted provided that the following conditions are met:
...
@@ -116,6 +116,18 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
...
@@ -116,6 +116,18 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
driver_data
=
plat_driver_data
;
driver_data
=
plat_driver_data
;
/*
* The GIC driver data is initialized by the primary CPU with caches
* enabled. When the secondary CPU boots up, it initializes the
* GICC/GICR interface with the caches disabled. Hence flush the
* driver_data to ensure coherency. This is not required if the
* platform has HW_ASSISTED_COHERENCY enabled.
*/
#if !HW_ASSISTED_COHERENCY
flush_dcache_range
((
uintptr_t
)
&
driver_data
,
sizeof
(
driver_data
));
flush_dcache_range
((
uintptr_t
)
driver_data
,
sizeof
(
*
driver_data
));
#endif
INFO
(
"GICv3 %s legacy support detected."
INFO
(
"GICv3 %s legacy support detected."
" ARM GICV3 driver initialized in EL3
\n
"
,
" ARM GICV3 driver initialized in EL3
\n
"
,
gicv2_compat
?
"with"
:
"without"
);
gicv2_compat
?
"with"
:
"without"
);
...
...
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