diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
index e2c4513882703eacd0f2156589d0349fc56b5653..65f31e7fdf46cd7bbc42c510546c224f02dcfb27 100644
--- a/include/plat/common/common_def.h
+++ b/include/plat/common/common_def.h
@@ -119,22 +119,32 @@
*/
#if SEPARATE_CODE_AND_RODATA
#define BL_CODE_BASE (unsigned long)(&__TEXT_START__)
-#define BL_CODE_LIMIT (unsigned long)(&__TEXT_END__)
+#define BL_CODE_END (unsigned long)(&__TEXT_END__)
#define BL_RO_DATA_BASE (unsigned long)(&__RODATA_START__)
-#define BL_RO_DATA_LIMIT (unsigned long)(&__RODATA_END__)
+#define BL_RO_DATA_END (unsigned long)(&__RODATA_END__)
-#define BL1_CODE_LIMIT BL_CODE_LIMIT
+#define BL1_CODE_END BL_CODE_END
#define BL1_RO_DATA_BASE (unsigned long)(&__RODATA_START__)
-#define BL1_RO_DATA_LIMIT round_up(BL1_ROM_END, PAGE_SIZE)
+#define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE)
#else
#define BL_CODE_BASE (unsigned long)(&__RO_START__)
-#define BL_CODE_LIMIT (unsigned long)(&__RO_END__)
+#define BL_CODE_END (unsigned long)(&__RO_END__)
#define BL_RO_DATA_BASE 0
-#define BL_RO_DATA_LIMIT 0
+#define BL_RO_DATA_END 0
-#define BL1_CODE_LIMIT round_up(BL1_ROM_END, PAGE_SIZE)
+#define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE)
#define BL1_RO_DATA_BASE 0
-#define BL1_RO_DATA_LIMIT 0
+#define BL1_RO_DATA_END 0
#endif /* SEPARATE_CODE_AND_RODATA */
+/*
+ * The next 2 constants identify the extents of the coherent memory region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned. It is the responsibility of the linker script to ensure that
+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
+ * page-aligned addresses.
+ */
+#define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
+#define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__)
+
#endif /* __COMMON_DEF_H__ */
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 50d102afee631147152ad08f99a63a02afc4ff8e..81a87c440cb96f1ff6794d107f690d4563f77307 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -39,20 +39,6 @@
#include <xlat_tables.h>
#include "../../../bl1/bl1_private.h"
-
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl1_early_platform_setup
#pragma weak bl1_plat_arch_setup
@@ -124,12 +110,12 @@ void arm_bl1_plat_arch_setup(void)
arm_setup_page_tables(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL_CODE_BASE,
- BL1_CODE_LIMIT,
+ BL1_CODE_END,
BL1_RO_DATA_BASE,
- BL1_RO_DATA_LIMIT
+ BL1_RO_DATA_END
#if USE_COHERENT_MEM
- , BL1_COHERENT_RAM_BASE,
- BL1_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
#ifdef AARCH32
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index a4fac0da09fbd7d17c379ff0d4142770500fcf33..5f3070809308fb61102cf8e46751da04017389dd 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -39,18 +39,6 @@
#include <platform_def.h>
#include <string.h>
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
@@ -238,12 +226,12 @@ void arm_bl2_plat_arch_setup(void)
arm_setup_page_tables(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL_CODE_BASE,
- BL_CODE_LIMIT,
+ BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_LIMIT
+ BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c
index de7d0c2f9e582d3a3cb102b3efbac875f1ff92c3..86317f656c17539ba8d196f08f96a525cee5ef5d 100644
--- a/plat/arm/common/arm_bl2u_setup.c
+++ b/plat/arm/common/arm_bl2u_setup.c
@@ -36,18 +36,6 @@
#include <plat_arm.h>
#include <string.h>
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2U_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2U_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl2u_platform_setup
#pragma weak bl2u_early_platform_setup
@@ -95,13 +83,13 @@ void arm_bl2u_plat_arch_setup(void)
arm_setup_page_tables(BL2U_BASE,
BL31_LIMIT,
BL_CODE_BASE,
- BL_CODE_LIMIT,
+ BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_LIMIT
+ BL_RO_DATA_END
#if USE_COHERENT_MEM
,
- BL2U_COHERENT_RAM_BASE,
- BL2U_COHERENT_RAM_LIMIT
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
enable_mmu_el1(0);
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index bc1ec11ecd1fdba2a9e9f3e2f00d300a6b9433c8..d20d8cdd7cf955e5081537113efde7c38bb4f48e 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -41,18 +41,6 @@
#define BL31_END (uintptr_t)(&__BL31_END__)
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
-#endif
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
@@ -288,12 +276,12 @@ void arm_bl31_plat_arch_setup(void)
arm_setup_page_tables(BL31_BASE,
BL31_END - BL31_BASE,
BL_CODE_BASE,
- BL_CODE_LIMIT,
+ BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_LIMIT
+ BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
enable_mmu_el3(0);
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index d48556eeddbbfce8654de9c730c000fcfa4e81ae..a472ceb98476d735769761c67d5c11f6970ba93c 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -39,19 +39,6 @@
#define BL32_END (uintptr_t)(&__BL32_END__)
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL32_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
-#define BL32_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
-#endif
-
-
static entry_point_info_t bl33_image_ep_info;
/* Weak definitions may be overridden in specific ARM standard platform */
@@ -202,12 +189,12 @@ void sp_min_plat_arch_setup(void)
arm_setup_page_tables(BL32_BASE,
(BL32_END - BL32_BASE),
BL_CODE_BASE,
- BL_CODE_LIMIT,
+ BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_LIMIT
+ BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index 09029f4c2a1b5a7c7494c417b816de976c935be0..20533ac0febac9585dae83dd6e9f73e0849b7ab0 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -37,19 +37,6 @@
#define BL32_END (unsigned long)(&__BL32_END__)
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak tsp_early_platform_setup
#pragma weak tsp_platform_setup
@@ -91,12 +78,12 @@ void tsp_plat_arch_setup(void)
arm_setup_page_tables(BL32_BASE,
(BL32_END - BL32_BASE),
BL_CODE_BASE,
- BL_CODE_LIMIT,
+ BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_LIMIT
+ BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
#endif
);
enable_mmu_el1(0);
diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c
index 3a8612d34a871506103cf0293b0528e4ebb0b12c..af0858f0bbd1a10a1dbeae5653fdd1d4bba0c503 100644
--- a/plat/mediatek/mt6795/bl31_plat_setup.c
+++ b/plat/mediatek/mt6795/bl31_plat_setup.c
@@ -32,6 +32,7 @@
#include <arch_helpers.h>
#include <bl_common.h>
#include <cci.h>
+#include <common_def.h>
#include <console.h>
#include <context_mgmt.h>
#include <debug.h>
@@ -52,9 +53,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
-unsigned long __COHERENT_RAM_START__;
-unsigned long __COHERENT_RAM_END__;
-
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
@@ -64,16 +62,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
@@ -323,8 +311,8 @@ void bl31_plat_arch_setup(void)
(TZRAM_SIZE & ~(PAGE_SIZE_MASK)),
(BL31_RO_BASE & ~(PAGE_SIZE_MASK)),
BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
/* Initialize for ATF log buffer */
if (gteearg.atf_log_buf_size != 0) {
gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index 4626f81f3e67c97ea8057ee1e14e7d417b57284f..ef18d07955e043102f61eb90417ce2985aad1a4e 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -30,6 +30,7 @@
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
+#include <common_def.h>
#include <console.h>
#include <debug.h>
#include <generic_delay_timer.h>
@@ -47,9 +48,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
-unsigned long __COHERENT_RAM_START__;
-unsigned long __COHERENT_RAM_END__;
-
/*
* The next 3 constants identify the extents of the code, RO data region and the
* limit of the BL31 image. These addresses are used by the MMU setup code and
@@ -61,16 +59,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
@@ -191,10 +179,10 @@ void bl31_plat_arch_setup(void)
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
- (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
+ BL_COHERENT_RAM_END - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 7e2bebe25f0b5f0cdfa71ccb4ff4d6c13d26cd67..0fd7c821619ecce368df3d91de69e8d6874107c4 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -53,11 +53,6 @@ extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __BL31_END__;
-#if USE_COHERENT_MEM
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-#endif
-
extern uint64_t tegra_bl31_phys_base;
/*
@@ -71,18 +66,6 @@ extern uint64_t tegra_bl31_phys_base;
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
.tzdram_size = (uint64_t)TZDRAM_SIZE
@@ -212,8 +195,8 @@ void bl31_plat_arch_setup(void)
MT_MEMORY | MT_RO | MT_SECURE);
#if USE_COHERENT_MEM
- coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
- coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
+ coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
+ coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
mmap_add_region(coh_start, coh_start,
coh_size,
diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h
index d983ce6f076f80cac950d16e03971c96881f956b..1fa21642b610183c7458e3f284316951cd886dd7 100644
--- a/plat/qemu/include/platform_def.h
+++ b/plat/qemu/include/platform_def.h
@@ -175,7 +175,6 @@
#else
# error "Unsupported BL32_RAM_LOCATION_ID value"
#endif
-#define BL32_SIZE (BL32_LIMIT - BL32_BASE)
#define NS_IMAGE_OFFSET 0x60000000
diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c
index 4438aaccc5ffac9cb9dd3a3f8813f4a73870ac70..21217d70f5fce548fa1f58c5dd8773b7a6ece121 100644
--- a/plat/qemu/qemu_bl1_setup.c
+++ b/plat/qemu/qemu_bl1_setup.c
@@ -36,18 +36,6 @@
#include <platform_def.h>
#include "qemu_private.h"
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
-
/*******************************************************************************
* Declarations of linker defined symbols which will tell us where BL1 lives
* in Trusted RAM
@@ -98,7 +86,7 @@ void bl1_plat_arch_setup(void)
qemu_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL1_RO_BASE, BL1_RO_LIMIT,
- BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
void bl1_platform_setup(void)
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index 24da2b6fdfb00088ff29192c8ada5fe336923353..dba3beeb582f88226ba24797b4ba7912be71543b 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -46,16 +46,6 @@
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/*******************************************************************************
* This structure represents the superset of information that is passed to
* BL3-1, e.g. while passing control to it from BL2, bl31_params
@@ -216,7 +206,7 @@ void bl2_plat_arch_setup(void)
qemu_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE, BL2_RO_LIMIT,
- BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
/*******************************************************************************
diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c
index 7a48358c1ecb4bc06d95b13232488ced0dd999f1..547e13559f4d3846a3ed5f8a92a12525e4cfb721 100644
--- a/plat/qemu/qemu_bl31_setup.c
+++ b/plat/qemu/qemu_bl31_setup.c
@@ -46,16 +46,6 @@
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
@@ -105,7 +95,7 @@ void bl31_plat_arch_setup(void)
{
qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE),
BL31_RO_BASE, BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
static const unsigned int irq_sec_array[] = {
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index b073bde2fb3724cb0fa2c189cf714c4705f259d8..66678d3637e9b8158cbc9e2258002cfe3784bef6 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -46,9 +46,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
-unsigned long __COHERENT_RAM_START__;
-unsigned long __COHERENT_RAM_END__;
-
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
@@ -58,16 +55,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
@@ -144,9 +131,9 @@ void bl31_plat_arch_setup(void)
plat_cci_init();
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
- (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
+ BL_COHERENT_RAM_END - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index c05b094eb21538a3e5b046b19ea8f73c3795b932..c70fc3e4cdd0453c2dfe3e5720fc0ac6f7a1fd6c 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -40,16 +40,6 @@
#define BL31_END (unsigned long)(&__BL31_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -160,10 +150,10 @@ void bl31_plat_arch_setup(void)
arm_setup_page_tables(BL31_BASE,
BL31_END - BL31_BASE,
BL_CODE_BASE,
- BL_CODE_LIMIT,
+ BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_RO_DATA_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
enable_mmu_el3(0);
}
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index 8e3ca62494a7e032270be9724a7d3f1b4beab332..6feb5b9d1a89faa2fb7e81a8326153aad975122d 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -37,16 +37,6 @@
#define BL32_END (unsigned long)(&__BL32_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/*******************************************************************************
* Initialize the UART
******************************************************************************/
@@ -81,11 +71,11 @@ void tsp_plat_arch_setup(void)
arm_setup_page_tables(BL32_BASE,
BL32_END - BL32_BASE,
BL_CODE_BASE,
- BL_CODE_LIMIT,
+ BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_LIMIT,
- BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT
+ BL_RO_DATA_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
);
enable_mmu_el1(0);
}