From f3ec5c0cc9f950e13e18eb46c5029688e0f761b5 Mon Sep 17 00:00:00 2001 From: steven kao <skao@nvidia.com> Date: Sat, 23 Dec 2017 17:58:58 -0800 Subject: [PATCH] Tegra194: update scratch registers used to read boot parameters This patch changes SCRATCH_BOOT_PARAMS_ADDR macro to use SECURE_SCRATCH_RSV81 instead of SECURE_SCRATCH_RSV44. The previous level bootloader changed this setting, so update here to keep both components in sync. Change-Id: I4e0c1b54fc69482d5513a8608d0bf616677e1bdd Signed-off-by: steven kao <skao@nvidia.com> --- plat/nvidia/tegra/include/t194/tegra_def.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index e20b2c634..a98aa2da8 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -172,16 +172,16 @@ * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE U(0x0C390000) -#define SECURE_SCRATCH_RSV44_LO U(0x1C4) -#define SECURE_SCRATCH_RSV44_HI U(0x1C8) +#define SECURE_SCRATCH_RSV81_LO U(0x2EC) +#define SECURE_SCRATCH_RSV81_HI U(0x2F0) #define SECURE_SCRATCH_RSV97 U(0x36C) #define SECURE_SCRATCH_RSV99_LO U(0x37C) #define SECURE_SCRATCH_RSV99_HI U(0x380) #define SECURE_SCRATCH_RSV109_LO U(0x3CC) #define SECURE_SCRATCH_RSV109_HI U(0x3D0) -#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV44_LO -#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV44_HI +#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV81_LO +#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV81_HI #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 #define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO #define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI -- GitLab