mediatek: mt8192: enable NS access for systimer

Enable NS access for all systimers.
Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I3693997082a1d6f09fef5a79b6cf5a91be46cb8a

plat/mediatek/mt8192/bl31_plat_setup.c

@@ -17,6 +17,7 @@
 /* Platform Includes */
 #include <gpio/mtgpio.h>
 #include <mt_gic_v3.h>
+#include <mt_timer.h>
 #include <plat_params.h>
 #include <plat_private.h>
 
@@ -84,7 +85,9 @@ void bl31_platform_setup(void)
 	/* Initialize the GIC driver, CPU and distributor interfaces */
 	mt_gic_driver_init();
 	mt_gic_init();
+
 	plat_mt8192_gpio_init();
+	mt_systimer_init();
 }
 
 /*******************************************************************************

plat/mediatek/mt8192/drivers/timer/mt_timer.c

@@ -5,6 +5,7 @@
  */
 
 #include <arch_helpers.h>
+#include <lib/mmio.h>
 #include <mt_timer.h>
 #include <platform_def.h>
 
@@ -28,3 +29,10 @@ uint64_t sched_clock(void)
 		- normal_time_base;
 	return cval;
 }
+
+void mt_systimer_init(void)
+{
+	/* Enable access in NS mode */
+	mmio_write_32(CNTWACR_REG, CNT_WRITE_ACCESS_CTL_MASK);
+	mmio_write_32(CNTRACR_REG, CNT_READ_ACCESS_CTL_MASK);
+}

plat/mediatek/mt8192/drivers/timer/mt_timer.h

@@ -12,6 +12,8 @@
 #define CNTSR_REG           (SYSTIMER_BASE + 0x4)
 #define CNTSYS_L_REG        (SYSTIMER_BASE + 0x8)
 #define CNTSYS_H_REG        (SYSTIMER_BASE + 0xc)
+#define CNTWACR_REG         (SYSTIMER_BASE + 0x10)
+#define CNTRACR_REG         (SYSTIMER_BASE + 0x14)
 
 #define TIEO_EN             (1 << 3)
 #define COMP_15_EN          (1 << 10)
@@ -23,8 +25,11 @@
 #define COMP_20_MASK (COMP_20_EN | TIEO_EN)
 #define COMP_25_MASK (COMP_20_EN | COMP_25_EN)
 
+#define CNT_WRITE_ACCESS_CTL_MASK (0x3FFFFF0U)
+#define CNT_READ_ACCESS_CTL_MASK  (0x3FFFFFFU)
 
 void sched_clock_init(uint64_t normal_base, uint64_t atf_base);
 uint64_t sched_clock(void);
+void mt_systimer_init(void);
 
 #endif /* MT_TIMER_H */