From f9688f27551e938ae5d992f7859a9950a169b706 Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos <dimitris.papastamos@arm.com> Date: Tue, 13 Jun 2017 12:33:39 +0100 Subject: [PATCH] aarch32: Fix L2CTRL definition for Cortex A57 and A72 Fixes ARM-software/tf-issues#495 Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> --- include/lib/cpus/aarch32/cortex_a57.h | 2 +- include/lib/cpus/aarch32/cortex_a72.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index 1c3fa25cb..1486b9807 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -55,7 +55,7 @@ /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 3 +#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index a550192cd..59057bc5a 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -37,7 +37,7 @@ /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 3 +#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -- GitLab