From fee39236d254fb3103d0ec9e1c82eeda95558fcc Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 1 May 2014 14:34:59 +0100 Subject: [PATCH] juno: Fix the disable_mmu code Remove the hard coding of all the MMU related registers with 0 and disable MMU by clearing the M and C bit in SCTLR_ELx. Also remove use of partially qualified asm helper functions. Change-Id: I383083f93a0a53143e58f146faf7755198f6a6ca --- plat/juno/aarch64/plat_common.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/plat/juno/aarch64/plat_common.c b/plat/juno/aarch64/plat_common.c index 5de9e42e1..cd64598ae 100644 --- a/plat/juno/aarch64/plat_common.c +++ b/plat/juno/aarch64/plat_common.c @@ -89,11 +89,18 @@ void enable_mmu() void disable_mmu(void) { - /* Zero out the MMU related registers */ - write_mair(0); - write_tcr(0); - write_ttbr0(0); - write_sctlr(0); + unsigned long sctlr; + unsigned long current_el = read_current_el(); + + if (GET_EL(current_el) == MODE_EL3) { + sctlr = read_sctlr_el3(); + sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT); + write_sctlr_el3(sctlr); + } else { + sctlr = read_sctlr_el1(); + sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT); + write_sctlr_el1(sctlr); + } /* Flush the caches */ dcsw_op_all(DCCISW); -- GitLab