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Commit ff2743e5 authored by Anson Huang's avatar Anson Huang
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Support for NXP's i.MX8 SoCs IPC 



NXP's i.MX8 SoCs have system controller (M4 core)
which takes control of clock management, power management,
partition management, PAD management etc., other
clusters like Cortex-A35 can send out command via MU
(Message Unit) to system controller for clock/power
management etc..

This patch adds basic IPC(inter-processor communication) support.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
parent 841cb4f7
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plat/imx/common/include/imx8_iomux.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX8_IOMUX_H__
#define __IMX8_IOMUX_H__
#define PADRING_IFMUX_EN_SHIFT 31
#define PADRING_IFMUX_EN_MASK (1 << PADRING_IFMUX_EN_SHIFT)
#define PADRING_GP_EN_SHIFT 30
#define PADRING_GP_EN_MASK (1 << PADRING_GP_EN_SHIFT)
#define PADRING_IFMUX_SHIFT 27
#define PADRING_IFMUX_MASK (0x7 << PADRING_IFMUX_SHIFT)
#define PADRING_CONFIG_SHIFT 25
#define PADRING_CONFIG_MASK (0x3 << PADRING_CONFIG_SHIFT)
#define PADRING_LPCONFIG_SHIFT 23
#define PADRING_LPCONFIG_MASK (0x3 << PADRING_LPCONFIG_SHIFT)
#define PADRING_PULL_SHIFT 5
#define PADRING_PULL_MASK (0x3 << PADRING_PULL_SHIFT)
#define PADRING_DSE_SHIFT 0
#define PADRING_DSE_MASK (0x7 << PADRING_DSE_SHIFT)
#endif /* __IMX8_IOMUX_H__ */
plat/imx/common/include/sci/sci.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _SC_SCI_H
#define _SC_SCI_H
/* Defines */
/* Includes */
#include <sci/sci_ipc.h>
#include <sci/svc/pad/sci_pad_api.h>
#include <sci/svc/pm/sci_pm_api.h>
#include <sci/svc/rm/sci_rm_api.h>
#endif /* _SC_SCI_H */
plat/imx/common/include/sci/sci_ipc.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file for the IPC implementation.
*/
#ifndef SC_IPC_H
#define SC_IPC_H
/* Includes */
#include <sci/sci_types.h>
/* Defines */
/* Types */
/* Functions */
/*!
* This function opens an IPC channel.
*
* @param[out] ipc return pointer for ipc handle
* @param[in] id id of channel to open
*
* @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC
* otherwise).
*
* The \a id parameter is implementation specific. Could be an MU
* address, pointer to a driver path, channel index, etc.
*/
sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id);
/*!
* This function closes an IPC channel.
*
* @param[in] ipc id of channel to close
*/
void sc_ipc_close(sc_ipc_t ipc);
/*!
* This function reads a message from an IPC channel.
*
* @param[in] ipc id of channel read from
* @param[out] data pointer to message buffer to read
*
* This function will block if no message is available to be read.
*/
void sc_ipc_read(sc_ipc_t ipc, void *data);
/*!
* This function writes a message to an IPC channel.
*
* @param[in] ipc id of channel to write to
* @param[in] data pointer to message buffer to write
*
* This function will block if the outgoing buffer is full.
*/
void sc_ipc_write(sc_ipc_t ipc, void *data);
sc_ipc_t ipc_handle;
#endif /* SC_IPC_H */
plat/imx/common/include/sci/sci_rpc.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file for the RPC implementation.
*/
#ifndef SC_RPC_H
#define SC_RPC_H
/* Includes */
#include <sci/sci_types.h>
#include <sci/sci_ipc.h>
#include <stdbool.h>
/* Defines */
#define SC_RPC_VERSION 1U
#define SC_RPC_MAX_MSG 8U
#define RPC_VER(MSG) ((MSG)->version)
#define RPC_SIZE(MSG) ((MSG)->size)
#define RPC_SVC(MSG) ((MSG)->svc)
#define RPC_FUNC(MSG) ((MSG)->func)
#define RPC_R8(MSG) ((MSG)->func)
#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
#define SC_RPC_SVC_UNKNOWN 0U
#define SC_RPC_SVC_RETURN 1U
#define SC_RPC_SVC_PM 2U
#define SC_RPC_SVC_RM 3U
#define SC_RPC_SVC_TIMER 5U
#define SC_RPC_SVC_PAD 6U
#define SC_RPC_SVC_MISC 7U
#define SC_RPC_SVC_IRQ 8U
#define SC_RPC_SVC_ABORT 9U
#define SC_RPC_ASYNC_STATE_RD_START 0U
#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U
#define SC_RPC_ASYNC_STATE_RD_DONE 2U
#define SC_RPC_ASYNC_STATE_WR_START 3U
#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U
#define SC_RPC_ASYNC_STATE_WR_DONE 5U
#define SC_RPC_MU_GIR_SVC 0x1U
#define SC_RPC_MU_GIR_DBG 0x8U
/* Types */
typedef uint8_t sc_rpc_svc_t;
typedef struct sc_rpc_msg_s {
uint8_t version;
uint8_t size;
uint8_t svc;
uint8_t func;
union {
int32_t i32[(SC_RPC_MAX_MSG - 1U)];
int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U];
int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U];
uint32_t u32[(SC_RPC_MAX_MSG - 1U)];
uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U];
uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U];
} DATA;
} sc_rpc_msg_t;
typedef uint8_t sc_rpc_async_state_t;
typedef struct sc_rpc_async_msg_s {
sc_rpc_async_state_t state;
uint8_t wordIdx;
sc_rpc_msg_t msg;
uint32_t timeStamp;
} sc_rpc_async_msg_t;
/* Functions */
/*!
* This is an internal function to send an RPC message over an IPC
* channel. It is called by client-side SCFW API function shims.
*
* @param[in] ipc IPC handle
* @param[in,out] msg handle to a message
* @param[in] no_resp response flag
*
* If \a no_resp is SC_FALSE then this function waits for a response
* and returns the result in \a msg.
*/
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
/*!
* This is an internal function to dispath an RPC call that has
* arrived via IPC over an MU. It is called by server-side SCFW.
*
* @param[in] mu MU message arrived on
* @param[in,out] msg handle to a message
*
* The function result is returned in \a msg.
*/
void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg);
/*!
* This function translates an RPC message and forwards on to the
* normal RPC API. It is used only by hypervisors.
*
* @param[in] ipc IPC handle
* @param[in,out] msg handle to a message
*
* This function decodes a message, calls macros to translate the
* resources, pads, addresses, partitions, memory regions, etc. and
* then forwards on to the hypervisors SCFW API.Return results are
* translated back abd placed back into the message to be returned
* to the original API.
*/
void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* SC_RPC_H */
plat/imx/common/include/sci/sci_scfw.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _SC_SCFW_H
#define _SC_SCFW_H
/* Includes */
#include <types.h>
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*!
* This type is used to declare a handle for an IPC communication
* channel. Its meaning is specific to the IPC implementation.
*/
typedef uint64_t sc_ipc_t;
/*!
* This type is used to declare an ID for an IPC communication
* channel. For the reference IPC implementation, this ID
* selects the base address of the MU used for IPC.
*/
typedef uint64_t sc_ipc_id_t;
#endif /* _SC_SCFW_H */
plat/imx/common/include/sci/sci_types.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file containing types used across multiple service APIs.
*/
#ifndef SC_TYPES_H
#define SC_TYPES_H
/* Includes */
#include <sci/sci_scfw.h>
/* Defines */
/*!
* @name Defines for common frequencies
*/
/*@{*/
#define SC_32KHZ 32768U /* 32KHz */
#define SC_10MHZ 10000000U /* 10MHz */
#define SC_20MHZ 20000000U /* 20MHz */
#define SC_25MHZ 25000000U /* 25MHz */
#define SC_27MHZ 27000000U /* 27MHz */
#define SC_40MHZ 40000000U /* 40MHz */
#define SC_45MHZ 45000000U /* 45MHz */
#define SC_50MHZ 50000000U /* 50MHz */
#define SC_60MHZ 60000000U /* 60MHz */
#define SC_66MHZ 66666666U /* 66MHz */
#define SC_74MHZ 74250000U /* 74.25MHz */
#define SC_80MHZ 80000000U /* 80MHz */
#define SC_83MHZ 83333333U /* 83MHz */
#define SC_84MHZ 84375000U /* 84.37MHz */
#define SC_100MHZ 100000000U /* 100MHz */
#define SC_125MHZ 125000000U /* 125MHz */
#define SC_133MHZ 133333333U /* 133MHz */
#define SC_135MHZ 135000000U /* 135MHz */
#define SC_150MHZ 150000000U /* 150MHz */
#define SC_160MHZ 160000000U /* 160MHz */
#define SC_166MHZ 166666666U /* 166MHz */
#define SC_175MHZ 175000000U /* 175MHz */
#define SC_180MHZ 180000000U /* 180MHz */
#define SC_200MHZ 200000000U /* 200MHz */
#define SC_250MHZ 250000000U /* 250MHz */
#define SC_266MHZ 266666666U /* 266MHz */
#define SC_300MHZ 300000000U /* 300MHz */
#define SC_312MHZ 312500000U /* 312.5MHZ */
#define SC_320MHZ 320000000U /* 320MHz */
#define SC_325MHZ 325000000U /* 325MHz */
#define SC_333MHZ 333333333U /* 333MHz */
#define SC_350MHZ 350000000U /* 350MHz */
#define SC_372MHZ 372000000U /* 372MHz */
#define SC_375MHZ 375000000U /* 375MHz */
#define SC_400MHZ 400000000U /* 400MHz */
#define SC_500MHZ 500000000U /* 500MHz */
#define SC_594MHZ 594000000U /* 594MHz */
#define SC_625MHZ 625000000U /* 625MHz */
#define SC_640MHZ 640000000U /* 640MHz */
#define SC_650MHZ 650000000U /* 650MHz */
#define SC_667MHZ 666666667U /* 667MHz */
#define SC_675MHZ 675000000U /* 675MHz */
#define SC_700MHZ 700000000U /* 700MHz */
#define SC_720MHZ 720000000U /* 720MHz */
#define SC_750MHZ 750000000U /* 750MHz */
#define SC_800MHZ 800000000U /* 800MHz */
#define SC_850MHZ 850000000U /* 850MHz */
#define SC_900MHZ 900000000U /* 900MHz */
#define SC_1000MHZ 1000000000U /* 1GHz */
#define SC_1056MHZ 1056000000U /* 1.056GHz */
#define SC_1188MHZ 1188000000U /* 1.188GHz */
#define SC_1260MHZ 1260000000U /* 1.26GHz */
#define SC_1280MHZ 1280000000U /* 1.28GHz */
#define SC_1300MHZ 1300000000U /* 1.3GHz */
#define SC_1400MHZ 1400000000U /* 1.4GHz */
#define SC_1500MHZ 1500000000U /* 1.5GHz */
#define SC_1600MHZ 1600000000U /* 1.6GHz */
#define SC_1800MHZ 1800000000U /* 1.8GHz */
#define SC_2000MHZ 2000000000U /* 2.0GHz */
#define SC_2112MHZ 2112000000U /* 2.12GHz */
/*@}*/
/*!
* @name Defines for 24M related frequencies
*/
/*@{*/
#define SC_8MHZ 8000000U /* 8MHz */
#define SC_12MHZ 12000000U /* 12MHz */
#define SC_19MHZ 19800000U /* 19.8MHz */
#define SC_24MHZ 24000000U /* 24MHz */
#define SC_48MHZ 48000000U /* 48MHz */
#define SC_120MHZ 120000000U /* 120MHz */
#define SC_132MHZ 132000000U /* 132MHz */
#define SC_144MHZ 144000000U /* 144MHz */
#define SC_192MHZ 192000000U /* 192MHz */
#define SC_211MHZ 211200000U /* 211.2MHz */
#define SC_240MHZ 240000000U /* 240MHz */
#define SC_264MHZ 264000000U /* 264MHz */
#define SC_352MHZ 352000000U /* 352MHz */
#define SC_360MHZ 360000000U /* 360MHz */
#define SC_384MHZ 384000000U /* 384MHz */
#define SC_396MHZ 396000000U /* 396MHz */
#define SC_432MHZ 432000000U /* 432MHz */
#define SC_480MHZ 480000000U /* 480MHz */
#define SC_600MHZ 600000000U /* 600MHz */
#define SC_744MHZ 744000000U /* 744MHz */
#define SC_792MHZ 792000000U /* 792MHz */
#define SC_864MHZ 864000000U /* 864MHz */
#define SC_960MHZ 960000000U /* 960MHz */
#define SC_1056MHZ 1056000000U /* 1056MHz */
#define SC_1200MHZ 1200000000U /* 1.2GHz */
#define SC_1464MHZ 1464000000U /* 1.464GHz */
#define SC_2400MHZ 2400000000U /* 2.4GHz */
/*@}*/
/*!
* @name Defines for A/V related frequencies
*/
/*@{*/
#define SC_62MHZ 62937500U /* 62.9375MHz */
#define SC_755MHZ 755250000U /* 755.25MHz */
/*@}*/
/*!
* @name Defines for type widths
*/
/*@{*/
#define SC_FADDR_W 36U /* Width of sc_faddr_t */
#define SC_BOOL_W 1U /* Width of sc_bool_t */
#define SC_ERR_W 4U /* Width of sc_err_t */
#define SC_RSRC_W 10U /* Width of sc_rsrc_t */
#define SC_CTRL_W 6U /* Width of sc_ctrl_t */
/*@}*/
/*!
* @name Defines for sc_bool_t
*/
/*@{*/
#define SC_FALSE ((sc_bool_t) 0U) /* True */
#define SC_TRUE ((sc_bool_t) 1U) /* False */
/*@}*/
/*!
* @name Defines for sc_err_t.
*/
/*@{*/
#define SC_ERR_NONE 0U /* Success */
#define SC_ERR_VERSION 1U /* Incompatible API version */
#define SC_ERR_CONFIG 2U /* Configuration error */
#define SC_ERR_PARM 3U /* Bad parameter */
#define SC_ERR_NOACCESS 4U /* Permission error (no access) */
#define SC_ERR_LOCKED 5U /* Permission error (locked) */
#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */
#define SC_ERR_NOTFOUND 7U /* Not found */
#define SC_ERR_NOPOWER 8U /* No power */
#define SC_ERR_IPC 9U /* Generic IPC error */
#define SC_ERR_BUSY 10U /* Resource is currently busy/active */
#define SC_ERR_FAIL 11U /* General I/O failure */
#define SC_ERR_LAST 12U
/*@}*/
/*!
* @name Defines for sc_rsrc_t.
*/
/*@{*/
#define SC_R_A53 0U
#define SC_R_A53_0 1U
#define SC_R_A53_1 2U
#define SC_R_A53_2 3U
#define SC_R_A53_3 4U
#define SC_R_A72 5U
#define SC_R_A72_0 6U
#define SC_R_A72_1 7U
#define SC_R_A72_2 8U
#define SC_R_A72_3 9U
#define SC_R_CCI 10U
#define SC_R_DB 11U
#define SC_R_DRC_0 12U
#define SC_R_DRC_1 13U
#define SC_R_GIC_SMMU 14U
#define SC_R_IRQSTR_M4_0 15U
#define SC_R_IRQSTR_M4_1 16U
#define SC_R_SMMU 17U
#define SC_R_GIC 18U
#define SC_R_DC_0_BLIT0 19U
#define SC_R_DC_0_BLIT1 20U
#define SC_R_DC_0_BLIT2 21U
#define SC_R_DC_0_BLIT_OUT 22U
#define SC_R_DC_0_CAPTURE0 23U
#define SC_R_DC_0_CAPTURE1 24U
#define SC_R_DC_0_WARP 25U
#define SC_R_DC_0_INTEGRAL0 26U
#define SC_R_DC_0_INTEGRAL1 27U
#define SC_R_DC_0_VIDEO0 28U
#define SC_R_DC_0_VIDEO1 29U
#define SC_R_DC_0_FRAC0 30U
#define SC_R_DC_0_FRAC1 31U
#define SC_R_DC_0 32U
#define SC_R_GPU_2_PID0 33U
#define SC_R_DC_0_PLL_0 34U
#define SC_R_DC_0_PLL_1 35U
#define SC_R_DC_1_BLIT0 36U
#define SC_R_DC_1_BLIT1 37U
#define SC_R_DC_1_BLIT2 38U
#define SC_R_DC_1_BLIT_OUT 39U
#define SC_R_DC_1_CAPTURE0 40U
#define SC_R_DC_1_CAPTURE1 41U
#define SC_R_DC_1_WARP 42U
#define SC_R_DC_1_INTEGRAL0 43U
#define SC_R_DC_1_INTEGRAL1 44U
#define SC_R_DC_1_VIDEO0 45U
#define SC_R_DC_1_VIDEO1 46U
#define SC_R_DC_1_FRAC0 47U
#define SC_R_DC_1_FRAC1 48U
#define SC_R_DC_1 49U
#define SC_R_GPU_3_PID0 50U
#define SC_R_DC_1_PLL_0 51U
#define SC_R_DC_1_PLL_1 52U
#define SC_R_SPI_0 53U
#define SC_R_SPI_1 54U
#define SC_R_SPI_2 55U
#define SC_R_SPI_3 56U
#define SC_R_UART_0 57U
#define SC_R_UART_1 58U
#define SC_R_UART_2 59U
#define SC_R_UART_3 60U
#define SC_R_UART_4 61U
#define SC_R_EMVSIM_0 62U
#define SC_R_EMVSIM_1 63U
#define SC_R_DMA_0_CH0 64U
#define SC_R_DMA_0_CH1 65U
#define SC_R_DMA_0_CH2 66U
#define SC_R_DMA_0_CH3 67U
#define SC_R_DMA_0_CH4 68U
#define SC_R_DMA_0_CH5 69U
#define SC_R_DMA_0_CH6 70U
#define SC_R_DMA_0_CH7 71U
#define SC_R_DMA_0_CH8 72U
#define SC_R_DMA_0_CH9 73U
#define SC_R_DMA_0_CH10 74U
#define SC_R_DMA_0_CH11 75U
#define SC_R_DMA_0_CH12 76U
#define SC_R_DMA_0_CH13 77U
#define SC_R_DMA_0_CH14 78U
#define SC_R_DMA_0_CH15 79U
#define SC_R_DMA_0_CH16 80U
#define SC_R_DMA_0_CH17 81U
#define SC_R_DMA_0_CH18 82U
#define SC_R_DMA_0_CH19 83U
#define SC_R_DMA_0_CH20 84U
#define SC_R_DMA_0_CH21 85U
#define SC_R_DMA_0_CH22 86U
#define SC_R_DMA_0_CH23 87U
#define SC_R_DMA_0_CH24 88U
#define SC_R_DMA_0_CH25 89U
#define SC_R_DMA_0_CH26 90U
#define SC_R_DMA_0_CH27 91U
#define SC_R_DMA_0_CH28 92U
#define SC_R_DMA_0_CH29 93U
#define SC_R_DMA_0_CH30 94U
#define SC_R_DMA_0_CH31 95U
#define SC_R_I2C_0 96U
#define SC_R_I2C_1 97U
#define SC_R_I2C_2 98U
#define SC_R_I2C_3 99U
#define SC_R_I2C_4 100U
#define SC_R_ADC_0 101U
#define SC_R_ADC_1 102U
#define SC_R_FTM_0 103U
#define SC_R_FTM_1 104U
#define SC_R_CAN_0 105U
#define SC_R_CAN_1 106U
#define SC_R_CAN_2 107U
#define SC_R_DMA_1_CH0 108U
#define SC_R_DMA_1_CH1 109U
#define SC_R_DMA_1_CH2 110U
#define SC_R_DMA_1_CH3 111U
#define SC_R_DMA_1_CH4 112U
#define SC_R_DMA_1_CH5 113U
#define SC_R_DMA_1_CH6 114U
#define SC_R_DMA_1_CH7 115U
#define SC_R_DMA_1_CH8 116U
#define SC_R_DMA_1_CH9 117U
#define SC_R_DMA_1_CH10 118U
#define SC_R_DMA_1_CH11 119U
#define SC_R_DMA_1_CH12 120U
#define SC_R_DMA_1_CH13 121U
#define SC_R_DMA_1_CH14 122U
#define SC_R_DMA_1_CH15 123U
#define SC_R_DMA_1_CH16 124U
#define SC_R_DMA_1_CH17 125U
#define SC_R_DMA_1_CH18 126U
#define SC_R_DMA_1_CH19 127U
#define SC_R_DMA_1_CH20 128U
#define SC_R_DMA_1_CH21 129U
#define SC_R_DMA_1_CH22 130U
#define SC_R_DMA_1_CH23 131U
#define SC_R_DMA_1_CH24 132U
#define SC_R_DMA_1_CH25 133U
#define SC_R_DMA_1_CH26 134U
#define SC_R_DMA_1_CH27 135U
#define SC_R_DMA_1_CH28 136U
#define SC_R_DMA_1_CH29 137U
#define SC_R_DMA_1_CH30 138U
#define SC_R_DMA_1_CH31 139U
#define SC_R_UNUSED1 140U
#define SC_R_UNUSED2 141U
#define SC_R_UNUSED3 142U
#define SC_R_UNUSED4 143U
#define SC_R_GPU_0_PID0 144U
#define SC_R_GPU_0_PID1 145U
#define SC_R_GPU_0_PID2 146U
#define SC_R_GPU_0_PID3 147U
#define SC_R_GPU_1_PID0 148U
#define SC_R_GPU_1_PID1 149U
#define SC_R_GPU_1_PID2 150U
#define SC_R_GPU_1_PID3 151U
#define SC_R_PCIE_A 152U
#define SC_R_SERDES_0 153U
#define SC_R_MATCH_0 154U
#define SC_R_MATCH_1 155U
#define SC_R_MATCH_2 156U
#define SC_R_MATCH_3 157U
#define SC_R_MATCH_4 158U
#define SC_R_MATCH_5 159U
#define SC_R_MATCH_6 160U
#define SC_R_MATCH_7 161U
#define SC_R_MATCH_8 162U
#define SC_R_MATCH_9 163U
#define SC_R_MATCH_10 164U
#define SC_R_MATCH_11 165U
#define SC_R_MATCH_12 166U
#define SC_R_MATCH_13 167U
#define SC_R_MATCH_14 168U
#define SC_R_PCIE_B 169U
#define SC_R_SATA_0 170U
#define SC_R_SERDES_1 171U
#define SC_R_HSIO_GPIO 172U
#define SC_R_MATCH_15 173U
#define SC_R_MATCH_16 174U
#define SC_R_MATCH_17 175U
#define SC_R_MATCH_18 176U
#define SC_R_MATCH_19 177U
#define SC_R_MATCH_20 178U
#define SC_R_MATCH_21 179U
#define SC_R_MATCH_22 180U
#define SC_R_MATCH_23 181U
#define SC_R_MATCH_24 182U
#define SC_R_MATCH_25 183U
#define SC_R_MATCH_26 184U
#define SC_R_MATCH_27 185U
#define SC_R_MATCH_28 186U
#define SC_R_LCD_0 187U
#define SC_R_LCD_0_PWM_0 188U
#define SC_R_LCD_0_I2C_0 189U
#define SC_R_LCD_0_I2C_1 190U
#define SC_R_PWM_0 191U
#define SC_R_PWM_1 192U
#define SC_R_PWM_2 193U
#define SC_R_PWM_3 194U
#define SC_R_PWM_4 195U
#define SC_R_PWM_5 196U
#define SC_R_PWM_6 197U
#define SC_R_PWM_7 198U
#define SC_R_GPIO_0 199U
#define SC_R_GPIO_1 200U
#define SC_R_GPIO_2 201U
#define SC_R_GPIO_3 202U
#define SC_R_GPIO_4 203U
#define SC_R_GPIO_5 204U
#define SC_R_GPIO_6 205U
#define SC_R_GPIO_7 206U
#define SC_R_GPT_0 207U
#define SC_R_GPT_1 208U
#define SC_R_GPT_2 209U
#define SC_R_GPT_3 210U
#define SC_R_GPT_4 211U
#define SC_R_KPP 212U
#define SC_R_MU_0A 213U
#define SC_R_MU_1A 214U
#define SC_R_MU_2A 215U
#define SC_R_MU_3A 216U
#define SC_R_MU_4A 217U
#define SC_R_MU_5A 218U
#define SC_R_MU_6A 219U
#define SC_R_MU_7A 220U
#define SC_R_MU_8A 221U
#define SC_R_MU_9A 222U
#define SC_R_MU_10A 223U
#define SC_R_MU_11A 224U
#define SC_R_MU_12A 225U
#define SC_R_MU_13A 226U
#define SC_R_MU_5B 227U
#define SC_R_MU_6B 228U
#define SC_R_MU_7B 229U
#define SC_R_MU_8B 230U
#define SC_R_MU_9B 231U
#define SC_R_MU_10B 232U
#define SC_R_MU_11B 233U
#define SC_R_MU_12B 234U
#define SC_R_MU_13B 235U
#define SC_R_ROM_0 236U
#define SC_R_FSPI_0 237U
#define SC_R_FSPI_1 238U
#define SC_R_IEE 239U
#define SC_R_IEE_R0 240U
#define SC_R_IEE_R1 241U
#define SC_R_IEE_R2 242U
#define SC_R_IEE_R3 243U
#define SC_R_IEE_R4 244U
#define SC_R_IEE_R5 245U
#define SC_R_IEE_R6 246U
#define SC_R_IEE_R7 247U
#define SC_R_SDHC_0 248U
#define SC_R_SDHC_1 249U
#define SC_R_SDHC_2 250U
#define SC_R_ENET_0 251U
#define SC_R_ENET_1 252U
#define SC_R_MLB_0 253U
#define SC_R_DMA_2_CH0 254U
#define SC_R_DMA_2_CH1 255U
#define SC_R_DMA_2_CH2 256U
#define SC_R_DMA_2_CH3 257U
#define SC_R_DMA_2_CH4 258U
#define SC_R_USB_0 259U
#define SC_R_USB_1 260U
#define SC_R_USB_0_PHY 261U
#define SC_R_USB_2 262U
#define SC_R_USB_2_PHY 263U
#define SC_R_DTCP 264U
#define SC_R_NAND 265U
#define SC_R_LVDS_0 266U
#define SC_R_LVDS_0_PWM_0 267U
#define SC_R_LVDS_0_I2C_0 268U
#define SC_R_LVDS_0_I2C_1 269U
#define SC_R_LVDS_1 270U
#define SC_R_LVDS_1_PWM_0 271U
#define SC_R_LVDS_1_I2C_0 272U
#define SC_R_LVDS_1_I2C_1 273U
#define SC_R_LVDS_2 274U
#define SC_R_LVDS_2_PWM_0 275U
#define SC_R_LVDS_2_I2C_0 276U
#define SC_R_LVDS_2_I2C_1 277U
#define SC_R_M4_0_PID0 278U
#define SC_R_M4_0_PID1 279U
#define SC_R_M4_0_PID2 280U
#define SC_R_M4_0_PID3 281U
#define SC_R_M4_0_PID4 282U
#define SC_R_M4_0_RGPIO 283U
#define SC_R_M4_0_SEMA42 284U
#define SC_R_M4_0_TPM 285U
#define SC_R_M4_0_PIT 286U
#define SC_R_M4_0_UART 287U
#define SC_R_M4_0_I2C 288U
#define SC_R_M4_0_INTMUX 289U
#define SC_R_M4_0_SIM 290U
#define SC_R_M4_0_WDOG 291U
#define SC_R_M4_0_MU_0B 292U
#define SC_R_M4_0_MU_0A0 293U
#define SC_R_M4_0_MU_0A1 294U
#define SC_R_M4_0_MU_0A2 295U
#define SC_R_M4_0_MU_0A3 296U
#define SC_R_M4_0_MU_1A 297U
#define SC_R_M4_1_PID0 298U
#define SC_R_M4_1_PID1 299U
#define SC_R_M4_1_PID2 300U
#define SC_R_M4_1_PID3 301U
#define SC_R_M4_1_PID4 302U
#define SC_R_M4_1_RGPIO 303U
#define SC_R_M4_1_SEMA42 304U
#define SC_R_M4_1_TPM 305U
#define SC_R_M4_1_PIT 306U
#define SC_R_M4_1_UART 307U
#define SC_R_M4_1_I2C 308U
#define SC_R_M4_1_INTMUX 309U
#define SC_R_M4_1_SIM 310U
#define SC_R_M4_1_WDOG 311U
#define SC_R_M4_1_MU_0B 312U
#define SC_R_M4_1_MU_0A0 313U
#define SC_R_M4_1_MU_0A1 314U
#define SC_R_M4_1_MU_0A2 315U
#define SC_R_M4_1_MU_0A3 316U
#define SC_R_M4_1_MU_1A 317U
#define SC_R_SAI_0 318U
#define SC_R_SAI_1 319U
#define SC_R_SAI_2 320U
#define SC_R_IRQSTR_SCU2 321U
#define SC_R_IRQSTR_DSP 322U
#define SC_R_UNUSED5 323U
#define SC_R_OCRAM 324U
#define SC_R_AUDIO_PLL_0 325U
#define SC_R_PI_0 326U
#define SC_R_PI_0_PWM_0 327U
#define SC_R_PI_0_PWM_1 328U
#define SC_R_PI_0_I2C_0 329U
#define SC_R_PI_0_PLL 330U
#define SC_R_PI_1 331U
#define SC_R_PI_1_PWM_0 332U
#define SC_R_PI_1_PWM_1 333U
#define SC_R_PI_1_I2C_0 334U
#define SC_R_PI_1_PLL 335U
#define SC_R_SC_PID0 336U
#define SC_R_SC_PID1 337U
#define SC_R_SC_PID2 338U
#define SC_R_SC_PID3 339U
#define SC_R_SC_PID4 340U
#define SC_R_SC_SEMA42 341U
#define SC_R_SC_TPM 342U
#define SC_R_SC_PIT 343U
#define SC_R_SC_UART 344U
#define SC_R_SC_I2C 345U
#define SC_R_SC_MU_0B 346U
#define SC_R_SC_MU_0A0 347U
#define SC_R_SC_MU_0A1 348U
#define SC_R_SC_MU_0A2 349U
#define SC_R_SC_MU_0A3 350U
#define SC_R_SC_MU_1A 351U
#define SC_R_SYSCNT_RD 352U
#define SC_R_SYSCNT_CMP 353U
#define SC_R_DEBUG 354U
#define SC_R_SYSTEM 355U
#define SC_R_SNVS 356U
#define SC_R_OTP 357U
#define SC_R_VPU_PID0 358U
#define SC_R_VPU_PID1 359U
#define SC_R_VPU_PID2 360U
#define SC_R_VPU_PID3 361U
#define SC_R_VPU_PID4 362U
#define SC_R_VPU_PID5 363U
#define SC_R_VPU_PID6 364U
#define SC_R_VPU_PID7 365U
#define SC_R_VPU_UART 366U
#define SC_R_VPUCORE 367U
#define SC_R_VPUCORE_0 368U
#define SC_R_VPUCORE_1 369U
#define SC_R_VPUCORE_2 370U
#define SC_R_VPUCORE_3 371U
#define SC_R_DMA_4_CH0 372U
#define SC_R_DMA_4_CH1 373U
#define SC_R_DMA_4_CH2 374U
#define SC_R_DMA_4_CH3 375U
#define SC_R_DMA_4_CH4 376U
#define SC_R_ISI_CH0 377U
#define SC_R_ISI_CH1 378U
#define SC_R_ISI_CH2 379U
#define SC_R_ISI_CH3 380U
#define SC_R_ISI_CH4 381U
#define SC_R_ISI_CH5 382U
#define SC_R_ISI_CH6 383U
#define SC_R_ISI_CH7 384U
#define SC_R_MJPEG_DEC_S0 385U
#define SC_R_MJPEG_DEC_S1 386U
#define SC_R_MJPEG_DEC_S2 387U
#define SC_R_MJPEG_DEC_S3 388U
#define SC_R_MJPEG_ENC_S0 389U
#define SC_R_MJPEG_ENC_S1 390U
#define SC_R_MJPEG_ENC_S2 391U
#define SC_R_MJPEG_ENC_S3 392U
#define SC_R_MIPI_0 393U
#define SC_R_MIPI_0_PWM_0 394U
#define SC_R_MIPI_0_I2C_0 395U
#define SC_R_MIPI_0_I2C_1 396U
#define SC_R_MIPI_1 397U
#define SC_R_MIPI_1_PWM_0 398U
#define SC_R_MIPI_1_I2C_0 399U
#define SC_R_MIPI_1_I2C_1 400U
#define SC_R_CSI_0 401U
#define SC_R_CSI_0_PWM_0 402U
#define SC_R_CSI_0_I2C_0 403U
#define SC_R_CSI_1 404U
#define SC_R_CSI_1_PWM_0 405U
#define SC_R_CSI_1_I2C_0 406U
#define SC_R_HDMI 407U
#define SC_R_HDMI_I2S 408U
#define SC_R_HDMI_I2C_0 409U
#define SC_R_HDMI_PLL_0 410U
#define SC_R_HDMI_RX 411U
#define SC_R_HDMI_RX_BYPASS 412U
#define SC_R_HDMI_RX_I2C_0 413U
#define SC_R_ASRC_0 414U
#define SC_R_ESAI_0 415U
#define SC_R_SPDIF_0 416U
#define SC_R_SPDIF_1 417U
#define SC_R_SAI_3 418U
#define SC_R_SAI_4 419U
#define SC_R_SAI_5 420U
#define SC_R_GPT_5 421U
#define SC_R_GPT_6 422U
#define SC_R_GPT_7 423U
#define SC_R_GPT_8 424U
#define SC_R_GPT_9 425U
#define SC_R_GPT_10 426U
#define SC_R_DMA_2_CH5 427U
#define SC_R_DMA_2_CH6 428U
#define SC_R_DMA_2_CH7 429U
#define SC_R_DMA_2_CH8 430U
#define SC_R_DMA_2_CH9 431U
#define SC_R_DMA_2_CH10 432U
#define SC_R_DMA_2_CH11 433U
#define SC_R_DMA_2_CH12 434U
#define SC_R_DMA_2_CH13 435U
#define SC_R_DMA_2_CH14 436U
#define SC_R_DMA_2_CH15 437U
#define SC_R_DMA_2_CH16 438U
#define SC_R_DMA_2_CH17 439U
#define SC_R_DMA_2_CH18 440U
#define SC_R_DMA_2_CH19 441U
#define SC_R_DMA_2_CH20 442U
#define SC_R_DMA_2_CH21 443U
#define SC_R_DMA_2_CH22 444U
#define SC_R_DMA_2_CH23 445U
#define SC_R_DMA_2_CH24 446U
#define SC_R_DMA_2_CH25 447U
#define SC_R_DMA_2_CH26 448U
#define SC_R_DMA_2_CH27 449U
#define SC_R_DMA_2_CH28 450U
#define SC_R_DMA_2_CH29 451U
#define SC_R_DMA_2_CH30 452U
#define SC_R_DMA_2_CH31 453U
#define SC_R_ASRC_1 454U
#define SC_R_ESAI_1 455U
#define SC_R_SAI_6 456U
#define SC_R_SAI_7 457U
#define SC_R_AMIX 458U
#define SC_R_MQS_0 459U
#define SC_R_DMA_3_CH0 460U
#define SC_R_DMA_3_CH1 461U
#define SC_R_DMA_3_CH2 462U
#define SC_R_DMA_3_CH3 463U
#define SC_R_DMA_3_CH4 464U
#define SC_R_DMA_3_CH5 465U
#define SC_R_DMA_3_CH6 466U
#define SC_R_DMA_3_CH7 467U
#define SC_R_DMA_3_CH8 468U
#define SC_R_DMA_3_CH9 469U
#define SC_R_DMA_3_CH10 470U
#define SC_R_DMA_3_CH11 471U
#define SC_R_DMA_3_CH12 472U
#define SC_R_DMA_3_CH13 473U
#define SC_R_DMA_3_CH14 474U
#define SC_R_DMA_3_CH15 475U
#define SC_R_DMA_3_CH16 476U
#define SC_R_DMA_3_CH17 477U
#define SC_R_DMA_3_CH18 478U
#define SC_R_DMA_3_CH19 479U
#define SC_R_DMA_3_CH20 480U
#define SC_R_DMA_3_CH21 481U
#define SC_R_DMA_3_CH22 482U
#define SC_R_DMA_3_CH23 483U
#define SC_R_DMA_3_CH24 484U
#define SC_R_DMA_3_CH25 485U
#define SC_R_DMA_3_CH26 486U
#define SC_R_DMA_3_CH27 487U
#define SC_R_DMA_3_CH28 488U
#define SC_R_DMA_3_CH29 489U
#define SC_R_DMA_3_CH30 490U
#define SC_R_DMA_3_CH31 491U
#define SC_R_AUDIO_PLL_1 492U
#define SC_R_AUDIO_CLK_0 493U
#define SC_R_AUDIO_CLK_1 494U
#define SC_R_MCLK_OUT_0 495U
#define SC_R_MCLK_OUT_1 496U
#define SC_R_PMIC_0 497U
#define SC_R_PMIC_1 498U
#define SC_R_SECO 499U
#define SC_R_CAAM_JR1 500U
#define SC_R_CAAM_JR2 501U
#define SC_R_CAAM_JR3 502U
#define SC_R_SECO_MU_2 503U
#define SC_R_SECO_MU_3 504U
#define SC_R_SECO_MU_4 505U
#define SC_R_HDMI_RX_PWM_0 506U
#define SC_R_A35 507U
#define SC_R_A35_0 508U
#define SC_R_A35_1 509U
#define SC_R_A35_2 510U
#define SC_R_A35_3 511U
#define SC_R_DSP 512U
#define SC_R_DSP_RAM 513U
#define SC_R_CAAM_JR1_OUT 514U
#define SC_R_CAAM_JR2_OUT 515U
#define SC_R_CAAM_JR3_OUT 516U
#define SC_R_VPU_DEC_0 517U
#define SC_R_VPU_ENC_0 518U
#define SC_R_CAAM_JR0 519U
#define SC_R_CAAM_JR0_OUT 520U
#define SC_R_PMIC_2 521U
#define SC_R_DBLOGIC 522U
#define SC_R_HDMI_PLL_1 523U
#define SC_R_BOARD_R0 524U
#define SC_R_BOARD_R1 525U
#define SC_R_BOARD_R2 526U
#define SC_R_BOARD_R3 527U
#define SC_R_BOARD_R4 528U
#define SC_R_BOARD_R5 529U
#define SC_R_BOARD_R6 530U
#define SC_R_BOARD_R7 531U
#define SC_R_MJPEG_DEC_MP 532U
#define SC_R_MJPEG_ENC_MP 533U
#define SC_R_VPU_TS_0 534U
#define SC_R_VPU_MU_0 535U
#define SC_R_VPU_MU_1 536U
#define SC_R_VPU_MU_2 537U
#define SC_R_VPU_MU_3 538U
#define SC_R_VPU_ENC_1 539U
#define SC_R_VPU 540U
#define SC_R_LAST 541U
#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /* All resources */
/*@}*/
/* NOTE - please add by replacing some of the UNUSED from above! */
/*!
* Defnes for sc_ctrl_t.
*/
#define SC_C_TEMP 0U
#define SC_C_TEMP_HI 1U
#define SC_C_TEMP_LOW 2U
#define SC_C_PXL_LINK_MST1_ADDR 3U
#define SC_C_PXL_LINK_MST2_ADDR 4U
#define SC_C_PXL_LINK_MST_ENB 5U
#define SC_C_PXL_LINK_MST1_ENB 6U
#define SC_C_PXL_LINK_MST2_ENB 7U
#define SC_C_PXL_LINK_SLV1_ADDR 8U
#define SC_C_PXL_LINK_SLV2_ADDR 9U
#define SC_C_PXL_LINK_MST_VLD 10U
#define SC_C_PXL_LINK_MST1_VLD 11U
#define SC_C_PXL_LINK_MST2_VLD 12U
#define SC_C_SINGLE_MODE 13U
#define SC_C_ID 14U
#define SC_C_PXL_CLK_POLARITY 15U
#define SC_C_LINESTATE 16U
#define SC_C_PCIE_G_RST 17U
#define SC_C_PCIE_BUTTON_RST 18U
#define SC_C_PCIE_PERST 19U
#define SC_C_PHY_RESET 20U
#define SC_C_PXL_LINK_RATE_CORRECTION 21U
#define SC_C_PANIC 22U
#define SC_C_PRIORITY_GROUP 23U
#define SC_C_TXCLK 24U
#define SC_C_CLKDIV 25U
#define SC_C_DISABLE_50 26U
#define SC_C_DISABLE_125 27U
#define SC_C_SEL_125 28U
#define SC_C_MODE 29U
#define SC_C_SYNC_CTRL0 30U
#define SC_C_KACHUNK_CNT 31U
#define SC_C_KACHUNK_SEL 32U
#define SC_C_SYNC_CTRL1 33U
#define SC_C_DPI_RESET 34U
#define SC_C_MIPI_RESET 35U
#define SC_C_DUAL_MODE 36U
#define SC_C_VOLTAGE 37U
#define SC_C_PXL_LINK_SEL 38U
#define SC_C_OFS_SEL 39U
#define SC_C_OFS_AUDIO 40U
#define SC_C_OFS_PERIPH 41U
#define SC_C_OFS_IRQ 42U
#define SC_C_RST0 43U
#define SC_C_RST1 44U
#define SC_C_SEL0 45U
#define SC_C_LAST 46U
#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /* All pads */
/* Types */
/*!
* This type is used to store a boolean
*/
typedef uint8_t sc_bool_t;
/*!
* This type is used to store a system (full-size) address.
*/
typedef uint64_t sc_faddr_t;
/*!
* This type is used to indicate error response for most functions.
*/
typedef uint8_t sc_err_t;
/*!
* This type is used to indicate a resource. Resources include peripherals
* and bus masters (but not memory regions). Note items from list should
* never be changed or removed (only added to at the end of the list).
*/
typedef uint16_t sc_rsrc_t;
/*!
* This type is used to indicate a control.
*/
typedef uint8_t sc_ctrl_t;
/*!
* This type is used to indicate a pad. Valid values are SoC specific.
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
typedef uint16_t sc_pad_t;
/* Extra documentation of standard types */
#ifdef DOXYGEN
/*!
* Type used to declare an 8-bit integer.
*/
typedef __INT8_TYPE__ int8_t;
/*!
* Type used to declare a 16-bit integer.
*/
typedef __INT16_TYPE__ int16_t;
/*!
* Type used to declare a 32-bit integer.
*/
typedef __INT32_TYPE__ int32_t;
/*!
* Type used to declare a 64-bit integer.
*/
typedef __INT64_TYPE__ int64_t;
/*!
* Type used to declare an 8-bit unsigned integer.
*/
typedef __UINT8_TYPE__ uint8_t;
/*!
* Type used to declare a 16-bit unsigned integer.
*/
typedef __UINT16_TYPE__ uint16_t;
/*!
* Type used to declare a 32-bit unsigned integer.
*/
typedef __UINT32_TYPE__ uint32_t;
/*!
* Type used to declare a 64-bit unsigned integer.
*/
typedef __UINT64_TYPE__ uint64_t;
#endif
#endif /* SC_TYPES_H */
plat/imx/common/include/sci/svc/pad/sci_pad_api.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file containing the public API for the System Controller (SC)
* Pad Control (PAD) function.
*
* @addtogroup PAD_SVC (SVC) Pad Service
*
* Module for the Pad Control (PAD) service.
*
* @details
*
* Pad configuration is managed by SC firmware. The pad configuration
* features supported by the SC firmware include:
*
* - Configuring the mux, input/output connection, and low-power isolation
mode.
* - Configuring the technology-specific pad setting such as drive strength,
* pullup/pulldown, etc.
* - Configuring compensation for pad groups with dual voltage capability.
*
* Pad functions fall into one of three categories. Generic functions are
* common to all SoCs and all process technologies. SoC functions are raw
* low-level functions. Technology-specific functions are specific to the
* process technology.
*
* The list of pads is SoC specific. Refer to the SoC [Pad List](@ref PADS)
* for valid pad values. Note that all pads exist on a die but may or
* may not be brought out by the specific package. Mapping of pads to
* package pins/balls is documented in the associated Data Sheet. Some pads
* may not be brought out because the part (die+package) is defeatured and
* some pads may connect to the substrate in the package.
*
* Some pads (SC_P_COMP_*) that can be specified are not individual pads
* but are in fact pad groups. These groups have additional configuration
* that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More
* info on these can be found in the associated Reference Manual.
*
* Pads are managed as a resource by the Resource Manager (RM). They have
* assigned owners and only the owners can configure the pads. Some of the
* pads are reserved for use by the SCFW itself and this can be overriden
* with the implementation of board_config_sc(). Additionally, pads may
* be assigned to various other partitions via the implementation of
* board_system_config().
*
* Note muxing two input pads to the same IP functional signal will
* result in undefined behavior.
* @{
*/
#ifndef SC_PAD_API_H
#define SC_PAD_API_H
/* Includes */
#include <sci/sci_types.h>
#include <sci/svc/rm/sci_rm_api.h>
/* Defines */
/*!
* @name Defines for type widths
*/
/*@{*/
#define SC_PAD_MUX_W 3 /* Width of mux parameter */
/*@}*/
/*!
* @name Defines for sc_pad_config_t
*/
/*@{*/
#define SC_PAD_CONFIG_NORMAL 0U /* Normal */
#define SC_PAD_CONFIG_OD 1U /* Open Drain */
#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */
#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */
/*@}*/
/*!
* @name Defines for sc_pad_iso_t
*/
/*@{*/
#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */
#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */
#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */
#define SC_PAD_ISO_ON 3U /* ISO latched data is held */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_dse_t
*/
/*@{*/
#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed drive strength for 1.8v */
#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength for dual volt */
#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength for dual volt */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_ps_t
*/
/*@{*/
#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */
#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */
#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */
#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_pus_t
*/
/*@{*/
#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */
#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */
#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */
#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */
/*@}*/
/*!
* @name Defines for sc_pad_wakeup_t
*/
/*@{*/
#define SC_PAD_WAKEUP_OFF 0U /* Off */
#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */
#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */
#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */
#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */
#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */
/*@}*/
/* Types */
/*!
* This type is used to declare a pad config. It determines how the
* output data is driven, pull-up is controlled, and input signal is
* connected. Normal and OD are typical and only connect the input
* when the output is not driven. The IN options are less common and
* force an input connection even when driving the output.
*/
typedef uint8_t sc_pad_config_t;
/*!
* This type is used to declare a pad low-power isolation config.
* ISO_LATE is the most common setting. ISO_EARLY is only used when
* an output pad is directly determined by another input pad. The
* other two are only used when SW wants to directly contol isolation.
*/
typedef uint8_t sc_pad_iso_t;
/*!
* This type is used to declare a drive strength. Note it is specific
* to 28FDSOI. Also note that valid values depend on the pad type.
*/
typedef uint8_t sc_pad_28fdsoi_dse_t;
/*!
* This type is used to declare a pull select. Note it is specific
* to 28FDSOI.
*/
typedef uint8_t sc_pad_28fdsoi_ps_t;
/*!
* This type is used to declare a pull-up select. Note it is specific
* to 28FDSOI HSIC pads.
*/
typedef uint8_t sc_pad_28fdsoi_pus_t;
/*!
* This type is used to declare a wakeup mode of a pad.
*/
typedef uint8_t sc_pad_wakeup_t;
/* Functions */
/*!
* @name Generic Functions
* @{
*/
/*!
* This function configures the mux settings for a pad. This includes
* the signal mux, pad config, and low-power isolation mode.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to configure
* @param[in] mux mux setting
* @param[in] config pad config
* @param[in] iso low-power isolation mode
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Note muxing two input pads to the same IP functional signal will
* result in undefined behavior.
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
/*!
* This function gets the mux settings for a pad. This includes
* the signal mux, pad config, and low-power isolation mode.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to query
* @param[out] mux pointer to return mux setting
* @param[out] config pointer to return pad config
* @param[out] iso pointer to return low-power isolation mode
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *mux, sc_pad_config_t *config,
sc_pad_iso_t *iso);
/*!
* This function configures the general purpose pad control. This
* is technology dependent and includes things like drive strength,
* slew rate, pull up/down, etc. Refer to the SoC Reference Manual
* for bit field details.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to configure
* @param[in] ctrl control value to set
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl);
/*!
* This function gets the general purpose pad control. This
* is technology dependent and includes things like drive strength,
* slew rate, pull up/down, etc. Refer to the SoC Reference Manual
* for bit field details.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to query
* @param[out] ctrl pointer to return control value
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl);
/*!
* This function configures the wakeup mode of the pad.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to configure
* @param[in] wakeup wakeup to set
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup);
/*!
* This function gets the wakeup mode of a pad.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to query
* @param[out] wakeup pointer to return wakeup
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup);
/*!
* This function configures a pad.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to configure
* @param[in] mux mux setting
* @param[in] config pad config
* @param[in] iso low-power isolation mode
* @param[in] ctrl control value
* @param[in] wakeup wakeup to set
*
* @see sc_pad_set_mux().
* @see sc_pad_set_gp().
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Note muxing two input pads to the same IP functional signal will
* result in undefined behavior.
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
sc_pad_wakeup_t wakeup);
/*!
* This function gets a pad's config.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to query
* @param[out] mux pointer to return mux setting
* @param[out] config pointer to return pad config
* @param[out] iso pointer to return low-power isolation mode
* @param[out] ctrl pointer to return control value
* @param[out] wakeup pointer to return wakeup to set
*
* @see sc_pad_set_mux().
* @see sc_pad_set_gp().
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
sc_pad_config_t *config, sc_pad_iso_t *iso,
uint32_t *ctrl, sc_pad_wakeup_t *wakeup);
/* @} */
/*!
* @name SoC Specific Functions
* @{
*/
/*!
* This function configures the settings for a pad. This setting is SoC
* specific.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to configure
* @param[in] val value to set
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val);
/*!
* This function gets the settings for a pad. This setting is SoC
* specific.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to query
* @param[out] val pointer to return setting
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
/* @} */
/*!
* @name Technology Specific Functions
* @{
*/
/*!
* This function configures the pad control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to configure
* @param[in] dse drive strength
* @param[in] ps pull select
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse,
sc_pad_28fdsoi_ps_t ps);
/*!
* This function gets the pad control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to query
* @param[out] dse pointer to return drive strength
* @param[out] ps pointer to return pull select
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t *dse,
sc_pad_28fdsoi_ps_t *ps);
/*!
* This function configures the pad control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to configure
* @param[in] dse drive strength
* @param[in] hys hysteresis
* @param[in] pus pull-up select
* @param[in] pke pull keeper enable
* @param[in] pue pull-up enable
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
sc_bool_t pue);
/*!
* This function gets the pad control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to query
* @param[out] dse pointer to return drive strength
* @param[out] hys pointer to return hysteresis
* @param[out] pus pointer to return pull-up select
* @param[out] pke pointer to return pull keeper enable
* @param[out] pue pointer to return pull-up enable
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke,
sc_bool_t *pue);
/*!
* This function configures the compensation control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to configure
* @param[in] compen compensation/freeze mode
* @param[in] fastfrz fast freeze
* @param[in] rasrcp compensation code for PMOS
* @param[in] rasrcn compensation code for NMOS
* @param[in] nasrc_sel NASRC read select
* @param[in] psw_ovr 2.5v override
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*
* Note \a psw_ovr is only applicable to pads supporting 2.5 volt
* operation (e.g. some Ethernet pads).
*/
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t compen, sc_bool_t fastfrz,
uint8_t rasrcp, uint8_t rasrcn,
sc_bool_t nasrc_sel, sc_bool_t psw_ovr);
/*!
* This function gets the compensation control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to query
* @param[out] compen pointer to return compensation/freeze mode
* @param[out] fastfrz pointer to return fast freeze
* @param[out] rasrcp pointer to return compensation code for PMOS
* @param[out] rasrcn pointer to return compensation code for NMOS
* @param[out] nasrc_sel pointer to return NASRC read select
* @param[out] compok pointer to return compensation status
* @param[out] nasrc pointer to return NASRCP/NASRCN
* @param[out] psw_ovr pointer to return the 2.5v override
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *compen, sc_bool_t *fastfrz,
uint8_t *rasrcp, uint8_t *rasrcn,
sc_bool_t *nasrc_sel, sc_bool_t *compok,
uint8_t *nasrc, sc_bool_t *psw_ovr);
/* @} */
#endif /* SC_PAD_API_H */
/**@}*/
plat/imx/common/include/sci/svc/pm/sci_pm_api.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file containing the public API for the System Controller (SC)
* Power Management (PM) function. This includes functions for power state
* control, clock control, reset control, and wake-up event control.
*
* @addtogroup PM_SVC (SVC) Power Management Service
*
* Module for the Power Management (PM) service.
*
* @{
*/
#ifndef SC_PM_API_H
#define SC_PM_API_H
/* Includes */
#include <sci/sci_types.h>
#include <sci/svc/rm/sci_rm_api.h>
/* Defines */
/*!
* @name Defines for type widths
*/
/*@{*/
#define SC_PM_POWER_MODE_W 2 /* Width of sc_pm_power_mode_t */
#define SC_PM_CLOCK_MODE_W 3 /* Width of sc_pm_clock_mode_t */
#define SC_PM_RESET_TYPE_W 2 /* Width of sc_pm_reset_type_t */
#define SC_PM_RESET_REASON_W 3 /* Width of sc_pm_reset_reason_t */
/*@}*/
/*!
* @name Defines for clock indexes (sc_pm_clk_t)
*/
/*@{*/
/*@}*/
/*!
* @name Defines for ALL parameters
*/
/*@{*/
#define SC_PM_CLK_ALL UINT8_MAX /* All clocks */
/*@}*/
/*!
* @name Defines for sc_pm_power_mode_t
*/
/*@{*/
#define SC_PM_PW_MODE_OFF 0U /* Power off */
#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
#define SC_PM_PW_MODE_LP 2U /* Power in low-power */
#define SC_PM_PW_MODE_ON 3U /* Power on */
/*@}*/
/*!
* @name Defines for sc_pm_clk_t
*/
/*@{*/
#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */
#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */
#define SC_PM_CLK_PER 2U /* Peripheral clock */
#define SC_PM_CLK_PHY 3U /* Phy clock */
#define SC_PM_CLK_MISC 4U /* Misc clock */
#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */
#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */
#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */
#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */
#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */
#define SC_PM_CLK_CPU 2U /* CPU clock */
#define SC_PM_CLK_PLL 4U /* PLL */
#define SC_PM_CLK_BYPASS 4U /* Bypass clock */
/*@}*/
/*!
* @name Defines for sc_pm_clk_mode_t
*/
/*@{*/
#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */
#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */
#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */
#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */
#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
/*@}*/
/*!
* @name Defines for sc_pm_clk_parent_t
*/
/*@{*/
#define SC_PM_PARENT_XTAL 0U /* Parent is XTAL. */
#define SC_PM_PARENT_PLL0 1U /* Parent is PLL0 */
#define SC_PM_PARENT_PLL1 2U /* Parent is PLL1 or PLL0/2 */
#define SC_PM_PARENT_PLL2 3U /* Parent in PLL2 or PLL0/4 */
#define SC_PM_PARENT_BYPS 4U /* Parent is a bypass clock. */
/*@}*/
/*!
* @name Defines for sc_pm_reset_type_t
*/
/*@{*/
#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */
#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */
#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */
/*@}*/
/*!
* @name Defines for sc_pm_reset_cause_t
*/
/*@{*/
#define SC_PM_RESET_CAUSE_TEMP 0U /* Reset due to temp panic alarm */
#define SC_PM_RESET_CAUSE_FAULT 1U /* Reset due to fault exception */
#define SC_PM_RESET_CAUSE_IRQ 2U /* Reset due to SCU reset IRQ */
#define SC_PM_RESET_CAUSE_WDOG 3U /* Reset due to SW WDOG */
#define SC_PM_RESET_CAUSE_API 4U /* Reset due to pm_reset() or monitor */
/*@}*/
/*!
* @name Defines for sc_pm_reset_reason_t
*/
/*@{*/
#define SC_PM_RESET_REASON_POR 0U /* Power on reset */
#define SC_PM_RESET_REASON_WARM 1U /* Warm reset */
#define SC_PM_RESET_REASON_SW 2U /* Software reset */
#define SC_PM_RESET_REASON_WDOG 3U /* Watchdog reset */
#define SC_PM_RESET_REASON_LOCKUP 4U /* Lockup reset */
#define SC_PM_RESET_REASON_TAMPER 5U /* Tamper reset */
#define SC_PM_RESET_REASON_TEMP 6U /* Temp reset */
#define SC_PM_RESET_REASON_LOW_VOLT 7U /* Low voltage reset */
/*@}*/
/*!
* @name Defines for sc_pm_sys_if_t
*/
/*@{*/
#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */
#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */
#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */
#define SC_PM_SYS_IF_DDR 3U /* DDR memory */
/*@}*/
/*!
* @name Defines for sc_pm_wake_src_t
*/
/*@{*/
#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */
#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */
/*@}*/
/* Types */
/*!
* This type is used to declare a power mode. Note resources only use
* SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
* as system power modes.
*/
typedef uint8_t sc_pm_power_mode_t;
/*!
* This type is used to declare a clock.
*/
typedef uint8_t sc_pm_clk_t;
/*!
* This type is used to declare a clock mode.
*/
typedef uint8_t sc_pm_clk_mode_t;
/*!
* This type is used to declare the clock parent.
*/
typedef uint8_t sc_pm_clk_parent_t;
/*!
* This type is used to declare clock rates.
*/
typedef uint32_t sc_pm_clock_rate_t;
/*!
* This type is used to declare a desired reset type.
*/
typedef uint8_t sc_pm_reset_type_t;
/*!
* This type is used to declare a desired reset type.
*/
typedef uint8_t sc_pm_reset_cause;
/*!
* This type is used to declare a reason for a reset.
*/
typedef uint8_t sc_pm_reset_reason_t;
/*!
* This type is used to specify a system-level interface to be power managed.
*/
typedef uint8_t sc_pm_sys_if_t;
/*!
* This type is used to specify a wake source for CPU resources.
*/
typedef uint8_t sc_pm_wake_src_t;
/* Functions */
/*!
* @name Power Functions
* @{
*/
/*!
* This function sets the system power mode. Only the owner of the
* SC_R_SYSTEM resource can do this.
*
* @param[in] ipc IPC handle
* @param[in] mode power mode to apply
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid mode,
* - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
*
* @see sc_pm_set_sys_power_mode().
*/
sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode);
/*!
* This function sets the power mode of a partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition
* @param[in] mode power mode to apply
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid partition or mode,
* - SC_ERR_NOACCESS if caller's partition is not the owner or
* parent of \a pt
*
* The power mode of the partitions is a max power any resource will
* be set to. Calling this will result in all resources owned
* by \a pt to have their power changed to the lower of \a mode or the
* individual resource mode set using sc_pm_set_resource_power_mode().
*/
sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_power_mode_t mode);
/*!
* This function gets the power mode of a partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition
* @param[out] mode pointer to return power mode
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid partition
*/
sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_power_mode_t *mode);
/*!
* This function sets the power mode of a resource.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] mode power mode to apply
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or mode,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner
*
* This function will record the individual resource power mode
* and change it if the requested mode is lower than or equal to the
* partition power mode set with sc_pm_set_partition_power_mode().
* In other words, the power mode of the resource will be the minimum
* of the resource power mode and the partition power mode.
*
* Note some resources are still not accessible even when powered up if bus
* transactions go through a fabric not powered up. Examples of this are
* resources in display and capture subsystems which require the display
* controller or the imaging subsytem to be powered up first.
*
* Not that resources are grouped into power domains by the underlying
* hardware. If any resource in the domain is on, the entire power domain
* will be on. Other power domains required to access the resource will
* also be turned on. Clocks required to access the peripheral will be
* turned on. Refer to the SoC RM for more info on power domains and access
* infrastructure (bus fabrics, clock domains, etc.).
*/
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode);
/*!
* This function gets the power mode of a resource.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[out] mode pointer to return power mode
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. The value
* returned does not reflect the power mode of the partition..
*/
sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t *mode);
/*!
* This function requests the low power mode some of the resources
* can enter based on their state. This API is only valid for the
* following resources : SC_R_A53, SC_R_A53_0, SC_R_A53_1, SC_A53_2,
* SC_A53_3, SC_R_A72, SC_R_A72_0, SC_R_A72_1, SC_R_CC1, SC_R_A35,
* SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3.
* For all other resources it will return SC_ERR_PARAM.
* This function will set the low power mode the cores, cluster
* and cluster associated resources will enter when all the cores
* in a given cluster execute WFI
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] mode power mode to apply
*
* @return Returns an error code (SC_ERR_NONE = success).
*
*/
sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode);
/*!
* This function requests low-power mode entry for CPU/cluster
* resources. This API is only valid for the following resources:
* SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x,
* SC_R_CCI. For all other resources it will return SC_ERR_PARAM.
* For individual core resources, the specified power mode
* and wake source will be applied after the core has entered
* WFI. For cluster resources, the specified power mode is
* applied after all cores in the cluster have entered low-power mode.
* For multicluster resources, the specified power mode is applied
* after all clusters have reached low-power mode.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] mode power mode to apply
* @param[in] wake_src wake source for low-power exit
*
* @return Returns an error code (SC_ERR_NONE = success).
*
*/
sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode,
sc_pm_wake_src_t wake_src);
/*!
* This function is used to set the resume address of a CPU.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the CPU resource
* @param[in] address 64-bit resume address
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or address,
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
* resource (CPU) owner
*/
sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
sc_faddr_t address);
/*!
* This function is used to set parameters for CPU resume from
* low-power mode.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the CPU resource
* @param[in] isPrimary set SC_TRUE if primary wake CPU
* @param[in] address 64-bit resume address
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or address,
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
* resource (CPU) owner
*/
sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
sc_bool_t isPrimary, sc_faddr_t address);
/*!
* This function requests the power mode configuration for system-level
* interfaces including messaging units, interconnect, and memories. This API
* is only valid for the following resources : SC_R_A53, SC_R_A72, and
* SC_R_M4_x_PID_y. For all other resources, it will return SC_ERR_PARAM.
* The requested power mode will be captured and applied to system-level
* resources as system conditions allow.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] sys_if system-level interface to be configured
* @param[in] hpm high-power mode for the system interface
* @param[in] lpm low-power mode for the system interface
*
* @return Returns an error code (SC_ERR_NONE = success).
*
*/
sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_sys_if_t sys_if,
sc_pm_power_mode_t hpm,
sc_pm_power_mode_t lpm);
/* @} */
/*!
* @name Clock/PLL Functions
* @{
*/
/*!
* This function sets the rate of a resource's clock/PLL.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] clk clock/PLL to affect
* @param[in,out] rate pointer to rate to set,
* return actual rate
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or clock/PLL,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner,
* - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource,
* - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL)
*
* Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
*/
sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
/*!
* This function gets the rate of a resource's clock/PLL.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] clk clock/PLL to affect
* @param[out] rate pointer to return rate
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or clock/PLL,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner,
* - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource
*
* Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
*/
sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
/*!
* This function enables/disables a resource's clock.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] clk clock to affect
* @param[in] enable enable if SC_TRUE; otherwise disabled
* @param[in] autog HW auto clock gating
*
* If \a resource is SC_R_ALL then all resources owned will be affected.
* No error will be returned.
*
* If \a clk is SC_PM_CLK_ALL, then an error will be returned if any
* of the available clocks returns an error.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or clock,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner,
* - SC_ERR_UNAVAILABLE if clock not applicable to this resource
*
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
*/
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
/*!
* This function sets the parent of a resource's clock.
* This function should only be called when the clock is disabled.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] clk clock to affect
* @param[in] parent New parent of the clock.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or clock,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner,
* - SC_ERR_UNAVAILABLE if clock not applicable to this resource
* - SC_ERR_BUSY if clock is currently enabled.
* - SC_ERR_NOPOWER if resource not powered
*
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
*/
sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
/*!
* This function gets the parent of a resource's clock.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] clk clock to affect
* @param[out] parent pointer to return parent of clock.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or clock,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner,
* - SC_ERR_UNAVAILABLE if clock not applicable to this resource
*
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
*/
sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/* @} */
/*!
* @name Reset Functions
* @{
*/
/*!
* This function is used to reset the system. Only the owner of the
* SC_R_SYSTEM resource can do this.
*
* @param[in] ipc IPC handle
* @param[in] type reset type
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid type,
* - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
*
* If this function returns, then the reset did not occur due to an
* invalid parameter.
*/
sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type);
/*!
* This function gets a caller's reset reason.
*
* @param[in] ipc IPC handle
* @param[out] reason pointer to return reset reason
*
* @return Returns an error code (SC_ERR_NONE = success).
*/
sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
/*!
* This function is used to boot a partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition to boot
* @param[in] resource_cpu ID of the CPU resource to start
* @param[in] boot_addr 64-bit boot address
* @param[in] resource_mu ID of the MU that must be powered
* @param[in] resource_dev ID of the boot device that must be powered
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid partition, resource, or addr,
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
* partition to boot
*/
sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
sc_rsrc_t resource_mu, sc_rsrc_t resource_dev);
/*!
* This function is used to reboot the caller's partition.
*
* @param[in] ipc IPC handle
* @param[in] type reset type
*
* If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by
* the calling partition will be reset if possible. SC state (partitions,
* power, clocks, etc.) is reset. The boot SW of the booting CPU must be
* able to handle peripherals that that are not reset.
*
* If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
* SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
* of the booting CPU must be able to handle peripherals and SC state that
* that are not reset.
*
* If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action.
*
* If this function returns, then the reset did not occur due to an
* invalid parameter.
*/
void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
/*!
* This function is used to reboot a partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition to reboot
* @param[in] type reset type
*
* If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by
* the calling partition will be reset if possible. SC state (partitions,
* power, clocks, etc.) is reset. The boot SW of the booting CPU must be
* able to handle peripherals that that are not reset.
*
* If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
* SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
* of the booting CPU must be able to handle peripherals and SC state that
* that are not reset.
*
* If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid partition or type
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
*
* Most peripherals owned by the partition will be reset if
* possible. SC state (partitions, power, clocks, etc.) is reset. The
* boot SW of the booting CPU must be able to handle peripherals that
* that are not reset.
*/
sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_reset_type_t type);
/*!
* This function is used to start/stop a CPU.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the CPU resource
* @param[in] enable start if SC_TRUE; otherwise stop
* @param[in] address 64-bit boot address
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or address,
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
* resource (CPU) owner
*/
sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
sc_faddr_t address);
/* @} */
#endif /* SC_PM_API_H */
/**@}*/
plat/imx/common/include/sci/svc/rm/sci_rm_api.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file containing the public API for the System Controller (SC)
* Resource Management (RM) function. This includes functions for
* partitioning resources, pads, and memory regions.
*
* @addtogroup RM_SVC (SVC) Resource Management Service
*
* Module for the Resource Management (RM) service.
*
* @includedoc rm/details.dox
*
* @{
*/
#ifndef SC_RM_API_H
#define SC_RM_API_H
/* Includes */
#include <sci/sci_types.h>
/* Defines */
/*!
* @name Defines for type widths
*/
/*@{*/
#define SC_RM_PARTITION_W 5 /* Width of sc_rm_pt_t */
#define SC_RM_MEMREG_W 6 /* Width of sc_rm_mr_t */
#define SC_RM_DID_W 4 /* Width of sc_rm_did_t */
#define SC_RM_SID_W 6 /* Width of sc_rm_sid_t */
#define SC_RM_SPA_W 2 /* Width of sc_rm_spa_t */
#define SC_RM_PERM_W 3 /* Width of sc_rm_perm_t */
/*@}*/
/*!
* @name Defines for ALL parameters
*/
/*@{*/
#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /* All partitions */
#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /* All memory regions */
/*@}*/
/*!
* @name Defines for sc_rm_spa_t
*/
/*@{*/
#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */
#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */
#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */
#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
/*@}*/
/*!
* @name Defines for sc_rm_perm_t
*/
/*@{*/
#define SC_RM_PERM_NONE 0U /* No access */
#define SC_RM_PERM_SEC_R 1U /* Secure RO */
#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */
#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */
#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
#define SC_RM_PERM_FULL 7U /* Full access */
/*@}*/
/* Types */
/*!
* This type is used to declare a resource partition.
*/
typedef uint8_t sc_rm_pt_t;
/*!
* This type is used to declare a memory region.
*/
typedef uint8_t sc_rm_mr_t;
/*!
* This type is used to declare a resource domain ID used by the
* isolation HW.
*/
typedef uint8_t sc_rm_did_t;
/*!
* This type is used to declare an SMMU StreamID.
*/
typedef uint16_t sc_rm_sid_t;
/*!
* This type is a used to declare master transaction attributes.
*/
typedef uint8_t sc_rm_spa_t;
/*!
* This type is used to declare a resource/memory region access permission.
* Refer to the XRDC2 Block Guide for more information.
*/
typedef uint8_t sc_rm_perm_t;
/* Functions */
/*!
* @name Partition Functions
* @{
*/
/*!
* This function requests that the SC create a new resource partition.
*
* @param[in] ipc IPC handle
* @param[out] pt return handle for partition; used for subsequent function
* calls associated with this partition
* @param[in] secure boolean indicating if this partition should be secure; only
* valid if caller is secure
* @param[in] isolated boolean indicating if this partition should be HW isolated
* via XRDC; set SC_TRUE if new DID is desired
* @param[in] restricted boolean indicating if this partition should be restricted; set
* SC_TRUE if masters in this partition cannot create new partitions
* @param[in] grant boolean indicating if this partition should always grant
* access and control to the parent
* @param[in] coherent boolean indicating if this partition is coherent;
* set SC_TRUE if only this partition will contain both AP clusters
* and they will be coherent via the CCI
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_ERR_PARM if caller's partition is not secure but a new secure partition is requested,
* - SC_ERR_LOCKED if caller's partition is locked,
* - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space)
*
* Marking as non-secure prevents subsequent functions from configuring masters in this
* partition to assert the secure signal. If restricted then the new partition is limited
* in what functions it can call, especially those associated with managing partitions.
*
* The grant option is usually used to isolate a bus master's traffic to specific
* memory without isolating the peripheral interface of the master or the API
* controls of that master.
*/
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
sc_bool_t isolated, sc_bool_t restricted,
sc_bool_t grant, sc_bool_t coherent);
/*!
* This function makes a partition confidential.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition that is granting
* @param[in] retro retroactive
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if \a pt out of range,
* - SC_ERR_NOACCESS if caller's not allowed to change \a pt
* - SC_ERR_LOCKED if partition \a pt is locked
*
* Call to make a partition confidential. Confidential means only this
* partition should be able to grant access permissions to this partition.
*
* If retroactive, then all resources owned by other partitions will have
* access rights for this partition removed, even if locked.
*/
sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro);
/*!
* This function frees a partition and assigns all resources to the caller.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition to free
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if \a pt out of range or invalid,
* - SC_ERR_NOACCESS if \a pt is the SC partition,
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
* - SC_ERR_LOCKED if \a pt or caller's partition is locked
*
* All resources, memory regions, and pads are assigned to the caller/parent.
* The partition watchdog is disabled (even if locked). DID is freed.
*/
sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
/*!
* This function returns the DID of a partition.
*
* @param[in] ipc IPC handle
*
* @return Returns the domain ID (DID) of the caller's partition.
*
* The DID is a SoC-specific internal ID used by the HW resource
* protection mechanism. It is only required by clients when using the
* SEMA42 module as the DID is sometimes connected to the master ID.
*/
sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc);
/*!
* This function forces a partition to use a specific static DID.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition to assign \a did
* @param[in] did static DID to assign
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if \a pt or \a did out of range,
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
* - SC_ERR_LOCKED if \a pt is locked
*
* Assumes no assigned resources or memory regions yet! The number of static
* DID is fixed by the SC at boot.
*/
sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did);
/*!
* This function locks a partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition to lock
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if \a pt out of range,
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt
*
* If a partition is locked it cannot be freed, have resources/pads assigned
* to/from it, memory regions created/assigned, DID changed, or parent changed.
*/
sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt);
/*!
* This function gets the partition handle of the caller.
*
* @param[in] ipc IPC handle
* @param[out] pt return handle for caller's partition
*
* @return Returns an error code (SC_ERR_NONE = success).
*/
sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
/*!
* This function sets a new parent for a partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition for which parent is to be
* changed
* @param[in] pt_parent handle of partition to set as parent
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
* - SC_ERR_LOCKED if either partition is locked
*/
sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
/*!
* This function moves all movable resources/pads owned by a source partition
* to a destination partition. It can be used to more quickly set up a new
* partition if a majority of the caller's resources are to be moved to a
* new partition.
*
* @param[in] ipc IPC handle
* @param[in] pt_src handle of partition from which resources should
* be moved from
* @param[in] pt_dst handle of partition to which resources should be
* moved to
* @param[in] move_rsrc boolean to indicate if resources should be moved
* @param[in] move_pads boolean to indicate if pads should be moved
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* By default, all resources are movable. This can be changed using the
* sc_rm_set_resource_movable() function. Note all masters defaulted to SMMU
* bypass.
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the
* parent of \a pt_src,
* - SC_ERR_LOCKED if either partition is locked
*/
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
sc_bool_t move_rsrc, sc_bool_t move_pads);
/* @} */
/*!
* @name Resource Functions
* @{
*/
/*!
* This function assigns ownership of a resource to a partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition to which resource should be
* assigned
* @param[in] resource resource to assign
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* This action resets the resource's master and peripheral attributes.
* Privilege attribute will be PASSTHRU, security attribute will be
* ASSERT if the partition si secure and NEGATE if it is not, and
* masters will defaulted to SMMU bypass. Access permissions will reset
* to SEC_RW for the owning partition only for secure partitions, FULL for
* non-secure. DEfault is no access by other partitions.
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
* of the owner,
* - SC_ERR_LOCKED if the owning partition or \a pt is locked
*/
sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
/*!
* This function flags resources as movable or not.
*
* @param[in] ipc IPC handle
* @param[in] resource_fst first resource for which flag should be set
* @param[in] resource_lst last resource for which flag should be set
* @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if resources are out of range,
* - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner,
* - SC_ERR_LOCKED if the owning partition is locked
*
* This function is used to determine the set of resources that will be
* moved using the sc_rm_move_all() function. All resources are movable
* by default so this function is normally used to prevent a set of
* resources from moving.
*/
sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
sc_rsrc_t resource_lst, sc_bool_t movable);
/*!
* This function flags all of a subsystem's resources as movable
* or not.
*
* @param[in] ipc IPC handle
* @param[in] resource resource to use to identify subsystem
* @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if a function argument is out of range
*
* Note \a resource is used to find the associated subsystem. Only
* resources owned by the caller are set.
*/
sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_bool_t movable);
/*!
* This function sets attributes for a resource which is a bus master (i.e.
* capable of DMA).
*
* @param[in] ipc IPC handle
* @param[in] resource master resource for which attributes should apply
* @param[in] sa security attribute
* @param[in] pa privilege attribute
* @param[in] smmu_bypass SMMU bypass mode
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner,
* - SC_ERR_LOCKED if the owning partition is locked
*
* This function configures how the HW isolation will see bus transactions
* from the specified master. Note the security attribute will only be
* changed if the caller's partition is secure.
*/
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_spa_t sa, sc_rm_spa_t pa,
sc_bool_t smmu_bypass);
/*!
* This function sets the StreamID for a resource which is a bus master (i.e.
* capable of DMA).
*
* @param[in] ipc IPC handle
* @param[in] resource master resource for which attributes should apply
* @param[in] sid StreamID
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
* of the owner,
* - SC_ERR_LOCKED if the owning partition is locked
*
* This function configures the SID attribute associated with all bus transactions
* from this master. Note 0 is not a valid SID as it is reserved to indicate
* bypass.
*/
sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_sid_t sid);
/*!
* This function sets access permissions for a peripheral resource.
*
* @param[in] ipc IPC handle
* @param[in] resource peripheral resource for which permissions should apply
* @param[in] pt handle of partition \a perm should by applied for
* @param[in] perm permissions to apply to \a resource for \a pt
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
* of the owner,
* - SC_ERR_LOCKED if the owning partition is locked
* - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
*
* This function configures how the HW isolation will restrict access to a
* peripheral based on the attributes of a transaction from bus master.
*/
sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_pt_t pt, sc_rm_perm_t perm);
/*!
* This function gets ownership status of a resource.
*
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
* @return Returns a boolean (SC_TRUE if caller's partition owns the resource).
*
* If \a resource is out of range then SC_FALSE is returned.
*/
sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to test if a resource is a bus master.
*
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
* @return Returns a boolean (SC_TRUE if the resource is a bus master).
*
* If \a resource is out of range then SC_FALSE is returned.
*/
sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to test if a resource is a peripheral.
*
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
* @return Returns a boolean (SC_TRUE if the resource is a peripheral).
*
* If \a resource is out of range then SC_FALSE is returned.
*/
sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to obtain info about a resource.
*
* @param[in] ipc IPC handle
* @param[in] resource resource to inquire about
* @param[out] sid pointer to return StreamID
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if \a resource is out of range
*/
sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_sid_t *sid);
/* @} */
/*!
* @name Memory Region Functions
* @{
*/
/*!
* This function requests that the SC create a new memory region.
*
* @param[in] ipc IPC handle
* @param[out] mr return handle for region; used for
* subsequent function calls
* associated with this region
* @param[in] addr_start start address of region (physical)
* @param[in] addr_end end address of region (physical)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if the new memory region is misaligned,
* - SC_ERR_LOCKED if caller's partition is locked,
* - SC_ERR_PARM if the new memory region spans multiple existing regions,
* - SC_ERR_NOACCESS if caller's partition does not own the memory containing
* the new region,
* - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
* space)
*
* The area covered by the memory region must currently be owned by the caller.
* By default, the new region will have access permission set to allow the
* caller to access.
*/
sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
sc_faddr_t addr_start, sc_faddr_t addr_end);
/*!
* This function requests that the SC split a memory region.
*
* @param[in] ipc IPC handle
* @param[in] mr handle of memory region to split
* @param[out] mr_ret return handle for new region; used for
* subsequent function calls
* associated with this region
* @param[in] addr_start start address of region (physical)
* @param[in] addr_end end address of region (physical)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if the new memory region is not start/end part of mr,
* - SC_ERR_LOCKED if caller's partition is locked,
* - SC_ERR_PARM if the new memory region spans multiple existing regions,
* - SC_ERR_NOACCESS if caller's partition does not own the memory containing
* the new region,
* - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
* space)
*
* Note the new region must start or end on the split region.
*/
sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
sc_faddr_t addr_end);
/*!
* This function frees a memory region.
*
* @param[in] ipc IPC handle
* @param[in] mr handle of memory region to free
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if \a mr out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr,
* - SC_ERR_LOCKED if the owning partition of \a mr is locked
*/
sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr);
/*!
* Internal SC function to find a memory region.
*
* @see sc_rm_find_memreg().
*/
/*!
* This function finds a memory region.
*
* @param[in] ipc IPC handle
* @param[out] mr return handle for region; used for
* subsequent function calls
* associated with this region
* @param[in] addr_start start address of region to search for
* @param[in] addr_end end address of region to search for
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOTFOUND if region not found,
*
* Searches only for regions owned by the caller. Finds first
* region containing the range specified.
*/
sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
sc_faddr_t addr_start, sc_faddr_t addr_end);
/*!
* This function assigns ownership of a memory region.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition to which memory region
* should be assigned
* @param[in] mr handle of memory region to assign
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent
* of the owner,
* - SC_ERR_LOCKED if the owning partition or \a pt is locked
*/
sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr);
/*!
* This function sets access permissions for a memory region.
*
* @param[in] ipc IPC handle
* @param[in] mr handle of memory region for which permissions
* should apply
* @param[in] pt handle of partition \a perm should by
* applied for
* @param[in] perm permissions to apply to \a mr for \a pt
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the region owner or parent
* of the owner,
* - SC_ERR_LOCKED if the owning partition is locked
* - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
*
* This function configures how the HW isolation will restrict access to a
* memory region based on the attributes of a transaction from bus master.
*/
sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_rm_pt_t pt, sc_rm_perm_t perm);
/*!
* This function gets ownership status of a memory region.
*
* @param[in] ipc IPC handle
* @param[in] mr handle of memory region to check
*
* @return Returns a boolean (SC_TRUE if caller's partition owns the
* memory region).
*
* If \a mr is out of range then SC_FALSE is returned.
*/
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
/*!
* This function is used to obtain info about a memory region.
*
* @param[in] ipc IPC handle
* @param[in] mr handle of memory region to inquire about
* @param[out] addr_start pointer to return start address
* @param[out] addr_end pointer to return end address
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if \a mr is out of range
*/
sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_faddr_t *addr_start, sc_faddr_t *addr_end);
/* @} */
/*!
* @name Pad Functions
* @{
*/
/*!
* This function assigns ownership of a pad to a partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of partition to which pad should
* be assigned
* @param[in] pad pad to assign
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent
* of the owner,
* - SC_ERR_LOCKED if the owning partition or \a pt is locked
*/
sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
/*!
* This function flags pads as movable or not.
*
* @param[in] ipc IPC handle
* @param[in] pad_fst first pad for which flag should be set
* @param[in] pad_lst last pad for which flag should be set
* @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if pads are out of range,
* - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner,
* - SC_ERR_LOCKED if the owning partition is locked
*
* This function is used to determine the set of pads that will be
* moved using the sc_rm_move_all() function. All pads are movable
* by default so this function is normally used to prevent a set of
* pads from moving.
*/
sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
sc_pad_t pad_lst, sc_bool_t movable);
/*!
* This function gets ownership status of a pad.
*
* @param[in] ipc IPC handle
* @param[in] pad pad to check
*
* @return Returns a boolean (SC_TRUE if caller's partition owns the pad).
*
* If \a pad is out of range then SC_FALSE is returned.
*/
sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
/* @} */
/*!
* @name Debug Functions
* @{
*/
/*!
* This function dumps the RM state for debug.
*
* @param[in] ipc IPC handle
*/
void sc_rm_dump(sc_ipc_t ipc);
/* @} */
#endif /* SC_RM_API_H */
/**@}*/
plat/imx/common/sci/imx8_mu.c 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <mmio.h>
#include "imx8_mu.h"
void MU_EnableRxFullInt(uint32_t base, uint32_t index)
{
uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
reg |= MU_CR_RIE0_MASK1 >> index;
mmio_write_32(base + MU_ACR_OFFSET1, reg);
}
void MU_EnableGeneralInt(uint32_t base, uint32_t index)
{
uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
reg |= MU_CR_GIE0_MASK1 >> index;
mmio_write_32(base + MU_ACR_OFFSET1, reg);
}
void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg)
{
uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
/* Wait TX register to be empty. */
while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
;
mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg);
}
void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg)
{
uint32_t mask = MU_SR_RF0_MASK1 >> regIndex;
/* Wait RX register to be full. */
while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
;
*msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4));
}
void MU_Init(uint32_t base)
{
uint32_t reg;
reg = mmio_read_32(base + MU_ACR_OFFSET1);
/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
| MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1);
mmio_write_32(base + MU_ACR_OFFSET1, reg);
}
plat/imx/common/sci/imx8_mu.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <types.h>
#define MU_ATR0_OFFSET1 0x0
#define MU_ARR0_OFFSET1 0x10
#define MU_ASR_OFFSET1 0x20
#define MU_ACR_OFFSET1 0x24
#define MU_TR_COUNT1 4
#define MU_RR_COUNT1 4
#define MU_CR_GIEn_MASK1 (0xF << 28)
#define MU_CR_RIEn_MASK1 (0xF << 24)
#define MU_CR_TIEn_MASK1 (0xF << 20)
#define MU_CR_GIRn_MASK1 (0xF << 16)
#define MU_CR_NMI_MASK1 (1 << 3)
#define MU_CR_Fn_MASK1 0x7
#define MU_SR_TE0_MASK1 (1 << 23)
#define MU_SR_RF0_MASK1 (1 << 27)
#define MU_CR_RIE0_MASK1 (1 << 27)
#define MU_CR_GIE0_MASK1 (1 << 31)
#define MU_TR_COUNT 4
#define MU_RR_COUNT 4
void MU_Init(uint32_t base);
void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg);
void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg);
void MU_EnableGeneralInt(uint32_t base, uint32_t index);
void MU_EnableRxFullInt(uint32_t base, uint32_t index);
plat/imx/common/sci/ipc.c 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <bakery_lock.h>
#include <sci/sci_scfw.h>
#include <sci/sci_ipc.h>
#include <sci/sci_rpc.h>
#include <stdlib.h>
#include "imx8_mu.h"
DEFINE_BAKERY_LOCK(sc_ipc_bakery_lock);
#define sc_ipc_lock_init() bakery_lock_init(&sc_ipc_bakery_lock)
#define sc_ipc_lock() bakery_lock_get(&sc_ipc_bakery_lock)
#define sc_ipc_unlock() bakery_lock_release(&sc_ipc_bakery_lock)
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp)
{
sc_ipc_lock();
sc_ipc_write(ipc, msg);
if (!no_resp)
sc_ipc_read(ipc, msg);
sc_ipc_unlock();
}
sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id)
{
uint32_t base = id;
uint32_t i;
/* Get MU base associated with IPC channel */
if ((ipc == NULL) || (base == 0))
return SC_ERR_IPC;
sc_ipc_lock_init();
/* Init MU */
MU_Init(base);
/* Enable all RX interrupts */
for (i = 0; i < MU_RR_COUNT; i++) {
MU_EnableRxFullInt(base, i);
}
/* Return MU address as handle */
*ipc = (sc_ipc_t) id;
return SC_ERR_NONE;
}
void sc_ipc_close(sc_ipc_t ipc)
{
uint32_t base = ipc;
if (base != 0)
MU_Init(base);
}
void sc_ipc_read(sc_ipc_t ipc, void *data)
{
uint32_t base = ipc;
sc_rpc_msg_t *msg = (sc_rpc_msg_t *) data;
uint8_t count = 0;
/* Check parms */
if ((base == 0) || (msg == NULL))
return;
/* Read first word */
MU_ReceiveMsg(base, 0, (uint32_t *) msg);
count++;
/* Check size */
if (msg->size > SC_RPC_MAX_MSG) {
*((uint32_t *) msg) = 0;
return;
}
/* Read remaining words */
while (count < msg->size) {
MU_ReceiveMsg(base, count % MU_RR_COUNT,
&(msg->DATA.u32[count - 1]));
count++;
}
}
void sc_ipc_write(sc_ipc_t ipc, void *data)
{
sc_rpc_msg_t *msg = (sc_rpc_msg_t *) data;
uint32_t base = ipc;
uint8_t count = 0;
/* Check parms */
if ((base == 0) || (msg == NULL))
return;
/* Check size */
if (msg->size > SC_RPC_MAX_MSG)
return;
/* Write first word */
MU_SendMessage(base, 0, *((uint32_t *) msg));
count++;
/* Write remaining words */
while (count < msg->size) {
MU_SendMessage(base, count % MU_TR_COUNT,
msg->DATA.u32[count - 1]);
count++;
}
}
plat/imx/common/sci/sci_api.mk 0 → 100644
View file @ ff2743e5
#
# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
BL31_SOURCES += plat/imx/common/sci/ipc.c \
plat/imx/common/sci/imx8_mu.c \
plat/imx/common/sci/svc/pad/pad_rpc_clnt.c \
plat/imx/common/sci/svc/pm/pm_rpc_clnt.c \
plat/imx/common/sci/svc/rm/rm_rpc_clnt.c
plat/imx/common/sci/svc/pad/pad_rpc_clnt.c 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* File containing client-side RPC functions for the PAD service. These
* functions are ported to clients that communicate to the SC.
*
* @addtogroup PAD_SVC
* @{
*/
/* Includes */
#include <sci/sci_types.h>
#include <sci/svc/rm/sci_rm_api.h>
#include <sci/svc/pad/sci_pad_api.h>
#include <sci/sci_rpc.h>
#include <stdlib.h>
#include "sci_pad_rpc.h"
/* Local Defines */
/* Local Types */
/* Local Functions */
sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_MUX;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_U8(&msg, 2U) = (uint8_t)mux;
RPC_U8(&msg, 3U) = (uint8_t)config;
RPC_U8(&msg, 4U) = (uint8_t)iso;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *mux, sc_pad_config_t *config,
sc_pad_iso_t *iso)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_MUX;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mux != NULL) {
*mux = RPC_U8(&msg, 0U);
}
if (config != NULL) {
*config = RPC_U8(&msg, 1U);
}
if (iso != NULL) {
*iso = RPC_U8(&msg, 2U);
}
return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP;
RPC_U32(&msg, 0U) = (uint32_t)ctrl;
RPC_U16(&msg, 4U) = (uint16_t)pad;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (ctrl != NULL) {
*ctrl = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_WAKEUP;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_U8(&msg, 2U) = (uint8_t)wakeup;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_WAKEUP;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (wakeup != NULL) {
*wakeup = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
sc_pad_wakeup_t wakeup)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_ALL;
RPC_U32(&msg, 0U) = (uint32_t)ctrl;
RPC_U16(&msg, 4U) = (uint16_t)pad;
RPC_U8(&msg, 6U) = (uint8_t)mux;
RPC_U8(&msg, 7U) = (uint8_t)config;
RPC_U8(&msg, 8U) = (uint8_t)iso;
RPC_U8(&msg, 9U) = (uint8_t)wakeup;
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
sc_pad_config_t *config, sc_pad_iso_t *iso,
uint32_t *ctrl, sc_pad_wakeup_t *wakeup)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_ALL;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (ctrl != NULL) {
*ctrl = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
if (mux != NULL) {
*mux = RPC_U8(&msg, 4U);
}
if (config != NULL) {
*config = RPC_U8(&msg, 5U);
}
if (iso != NULL) {
*iso = RPC_U8(&msg, 6U);
}
if (wakeup != NULL) {
*wakeup = RPC_U8(&msg, 7U);
}
return (sc_err_t)result;
}
sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET;
RPC_U32(&msg, 0U) = (uint32_t)val;
RPC_U16(&msg, 4U) = (uint16_t)pad;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (val != NULL) {
*val = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_U8(&msg, 2U) = (uint8_t)dse;
RPC_U8(&msg, 3U) = (uint8_t)ps;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t *dse,
sc_pad_28fdsoi_ps_t *ps)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (dse != NULL) {
*dse = RPC_U8(&msg, 0U);
}
if (ps != NULL) {
*ps = RPC_U8(&msg, 1U);
}
return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
sc_bool_t pue)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_HSIC;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_U8(&msg, 2U) = (uint8_t)dse;
RPC_U8(&msg, 3U) = (uint8_t)pus;
RPC_U8(&msg, 4U) = (uint8_t)hys;
RPC_U8(&msg, 5U) = (uint8_t)pke;
RPC_U8(&msg, 6U) = (uint8_t)pue;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke,
sc_bool_t *pue)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_HSIC;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (dse != NULL) {
*dse = RPC_U8(&msg, 0U);
}
if (pus != NULL) {
*pus = RPC_U8(&msg, 1U);
}
if (hys != NULL) {
*hys = RPC_U8(&msg, 2U);
}
if (pke != NULL) {
*pke = RPC_U8(&msg, 3U);
}
if (pue != NULL) {
*pue = RPC_U8(&msg, 4U);
}
return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t compen, sc_bool_t fastfrz,
uint8_t rasrcp, uint8_t rasrcn,
sc_bool_t nasrc_sel, sc_bool_t psw_ovr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_COMP;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_U8(&msg, 2U) = (uint8_t)compen;
RPC_U8(&msg, 3U) = (uint8_t)rasrcp;
RPC_U8(&msg, 4U) = (uint8_t)rasrcn;
RPC_U8(&msg, 5U) = (uint8_t)fastfrz;
RPC_U8(&msg, 6U) = (uint8_t)nasrc_sel;
RPC_U8(&msg, 7U) = (uint8_t)psw_ovr;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *compen, sc_bool_t *fastfrz,
uint8_t *rasrcp, uint8_t *rasrcn,
sc_bool_t *nasrc_sel, sc_bool_t *compok,
uint8_t *nasrc, sc_bool_t *psw_ovr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_COMP;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (compen != NULL) {
*compen = RPC_U8(&msg, 0U);
}
if (rasrcp != NULL) {
*rasrcp = RPC_U8(&msg, 1U);
}
if (rasrcn != NULL) {
*rasrcn = RPC_U8(&msg, 2U);
}
if (nasrc != NULL) {
*nasrc = RPC_U8(&msg, 3U);
}
if (fastfrz != NULL) {
*fastfrz = RPC_U8(&msg, 4U);
}
if (nasrc_sel != NULL) {
*nasrc_sel = RPC_U8(&msg, 5U);
}
if (compok != NULL) {
*compok = RPC_U8(&msg, 6U);
}
if (psw_ovr != NULL) {
*psw_ovr = RPC_U8(&msg, 7U);
}
return (sc_err_t)result;
}
/**@}*/
plat/imx/common/sci/svc/pad/sci_pad_rpc.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file for the PAD RPC implementation.
*
* @addtogroup PAD_SVC
* @{
*/
#ifndef SC_PAD_RPC_H
#define SC_PAD_RPC_H
/* Includes */
/* Defines */
/*!
* @name Defines for RPC PAD function calls
*/
/*@{*/
#define PAD_FUNC_UNKNOWN 0 /* Unknown function */
#define PAD_FUNC_SET_MUX 1U /* Index for pad_set_mux() RPC call */
#define PAD_FUNC_GET_MUX 6U /* Index for pad_get_mux() RPC call */
#define PAD_FUNC_SET_GP 2U /* Index for pad_set_gp() RPC call */
#define PAD_FUNC_GET_GP 7U /* Index for pad_get_gp() RPC call */
#define PAD_FUNC_SET_WAKEUP 4U /* Index for pad_set_wakeup() RPC call */
#define PAD_FUNC_GET_WAKEUP 9U /* Index for pad_get_wakeup() RPC call */
#define PAD_FUNC_SET_ALL 5U /* Index for pad_set_all() RPC call */
#define PAD_FUNC_GET_ALL 10U /* Index for pad_get_all() RPC call */
#define PAD_FUNC_SET 15U /* Index for pad_set() RPC call */
#define PAD_FUNC_GET 16U /* Index for pad_get() RPC call */
#define PAD_FUNC_SET_GP_28FDSOI 11U /* Index for pad_set_gp_28fdsoi() RPC call */
#define PAD_FUNC_GET_GP_28FDSOI 12U /* Index for pad_get_gp_28fdsoi() RPC call */
#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /* Index for pad_set_gp_28fdsoi_hsic() RPC call */
#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /* Index for pad_get_gp_28fdsoi_hsic() RPC call */
#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /* Index for pad_set_gp_28fdsoi_comp() RPC call */
#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /* Index for pad_get_gp_28fdsoi_comp() RPC call */
/*@}*/
/* Types */
/* Functions */
/*!
* This function dispatches an incoming PAD RPC request.
*
* @param[in] caller_pt caller partition
* @param[in] msg pointer to RPC message
*/
void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an PAD RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* SC_PAD_RPC_H */
/**@}*/
plat/imx/common/sci/svc/pm/pm_rpc_clnt.c 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* File containing client-side RPC functions for the PM service. These
* functions are ported to clients that communicate to the SC.
*
* @addtogroup PM_SVC
* @{
*/
/* Includes */
#include <sci/sci_types.h>
#include <sci/svc/rm/sci_rm_api.h>
#include <sci/svc/pm/sci_pm_api.h>
#include <sci/sci_rpc.h>
#include <stdlib.h>
#include "sci_pm_rpc.h"
/* Local Defines */
/* Local Types */
/* Local Functions */
sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_SYS_POWER_MODE;
RPC_U8(&msg, 0U) = (uint8_t)mode;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_power_mode_t mode)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_PARTITION_POWER_MODE;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_U8(&msg, 1U) = (uint8_t)mode;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_power_mode_t *mode)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_SYS_POWER_MODE;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mode != NULL) {
*mode = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_RESOURCE_POWER_MODE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)mode;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t *mode)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_RESOURCE_POWER_MODE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mode != NULL) {
*mode = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_LOW_POWER_MODE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)mode;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode,
sc_pm_wake_src_t wake_src)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_CPU_LOW_POWER_MODE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)mode;
RPC_U8(&msg, 3U) = (uint8_t)wake_src;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
sc_faddr_t address)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME_ADDR;
RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
RPC_U32(&msg, 4U) = (uint32_t)address;
RPC_U16(&msg, 8U) = (uint16_t)resource;
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
sc_bool_t isPrimary, sc_faddr_t address)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME;
RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
RPC_U32(&msg, 4U) = (uint32_t)address;
RPC_U16(&msg, 8U) = (uint16_t)resource;
RPC_U8(&msg, 10U) = (uint8_t)isPrimary;
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_sys_if_t sys_if,
sc_pm_power_mode_t hpm,
sc_pm_power_mode_t lpm)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_SYS_IF_POWER_MODE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)sys_if;
RPC_U8(&msg, 3U) = (uint8_t)hpm;
RPC_U8(&msg, 4U) = (uint8_t)lpm;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_RATE;
RPC_U32(&msg, 0U) = *(uint32_t *)rate;
RPC_U16(&msg, 4U) = (uint16_t)resource;
RPC_U8(&msg, 6U) = (uint8_t)clk;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
*rate = RPC_U32(&msg, 0U);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_RATE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)clk;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (rate != NULL) {
*rate = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CLOCK_ENABLE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)clk;
RPC_U8(&msg, 3U) = (uint8_t)enable;
RPC_U8(&msg, 4U) = (uint8_t)autog;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clk_parent_t parent)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_PARENT;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)clk;
RPC_U8(&msg, 3U) = (uint8_t)parent;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clk_parent_t *parent)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_PARENT;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)clk;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (parent != NULL) {
*parent = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET;
RPC_U8(&msg, 0U) = (uint8_t)type;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET_REASON;
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (reason != NULL) {
*reason = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
sc_rsrc_t resource_mu, sc_rsrc_t resource_dev)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_BOOT;
RPC_U32(&msg, 0U) = (uint32_t)(boot_addr >> 32U);
RPC_U32(&msg, 4U) = (uint32_t)boot_addr;
RPC_U16(&msg, 8U) = (uint16_t)resource_cpu;
RPC_U16(&msg, 10U) = (uint16_t)resource_mu;
RPC_U16(&msg, 12U) = (uint16_t)resource_dev;
RPC_U8(&msg, 14U) = (uint8_t)pt;
RPC_SIZE(&msg) = 5U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT;
RPC_U8(&msg, 0U) = (uint8_t)type;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_TRUE);
return;
}
sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_reset_type_t type)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT_PARTITION;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_U8(&msg, 1U) = (uint8_t)type;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
sc_faddr_t address)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CPU_START;
RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
RPC_U32(&msg, 4U) = (uint32_t)address;
RPC_U16(&msg, 8U) = (uint16_t)resource;
RPC_U8(&msg, 10U) = (uint8_t)enable;
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
/**@}*/
plat/imx/common/sci/svc/pm/sci_pm_rpc.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file for the PM RPC implementation.
*
* @addtogroup PM_SVC
* @{
*/
#ifndef SC_PM_RPC_H
#define SC_PM_RPC_H
/* Includes */
/* Defines */
/*!
* @name Defines for RPC PM function calls
*/
/*@{*/
#define PM_FUNC_UNKNOWN 0 /* Unknown function */
#define PM_FUNC_SET_SYS_POWER_MODE 19U /* Index for pm_set_sys_power_mode() RPC call */
#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /* Index for pm_set_partition_power_mode() RPC call */
#define PM_FUNC_GET_SYS_POWER_MODE 2U /* Index for pm_get_sys_power_mode() RPC call */
#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /* Index for pm_set_resource_power_mode() RPC call */
#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /* Index for pm_get_resource_power_mode() RPC call */
#define PM_FUNC_REQ_LOW_POWER_MODE 16U /* Index for pm_req_low_power_mode() RPC call */
#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /* Index for pm_req_cpu_low_power_mode() RPC call */
#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /* Index for pm_set_cpu_resume_addr() RPC call */
#define PM_FUNC_SET_CPU_RESUME 21U /* Index for pm_set_cpu_resume() RPC call */
#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /* Index for pm_req_sys_if_power_mode() RPC call */
#define PM_FUNC_SET_CLOCK_RATE 5U /* Index for pm_set_clock_rate() RPC call */
#define PM_FUNC_GET_CLOCK_RATE 6U /* Index for pm_get_clock_rate() RPC call */
#define PM_FUNC_CLOCK_ENABLE 7U /* Index for pm_clock_enable() RPC call */
#define PM_FUNC_SET_CLOCK_PARENT 14U /* Index for pm_set_clock_parent() RPC call */
#define PM_FUNC_GET_CLOCK_PARENT 15U /* Index for pm_get_clock_parent() RPC call */
#define PM_FUNC_RESET 13U /* Index for pm_reset() RPC call */
#define PM_FUNC_RESET_REASON 10U /* Index for pm_reset_reason() RPC call */
#define PM_FUNC_BOOT 8U /* Index for pm_boot() RPC call */
#define PM_FUNC_REBOOT 9U /* Index for pm_reboot() RPC call */
#define PM_FUNC_REBOOT_PARTITION 12U /* Index for pm_reboot_partition() RPC call */
#define PM_FUNC_CPU_START 11U /* Index for pm_cpu_start() RPC call */
/*@}*/
/* Types */
/* Functions */
/*!
* This function dispatches an incoming PM RPC request.
*
* @param[in] caller_pt caller partition
* @param[in] msg pointer to RPC message
*/
void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an PM RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* SC_PM_RPC_H */
/**@}*/
plat/imx/common/sci/svc/rm/rm_rpc_clnt.c 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* File containing client-side RPC functions for the RM service. These
* functions are ported to clients that communicate to the SC.
*
* @addtogroup RM_SVC
* @{
*/
/* Includes */
#include <sci/sci_types.h>
#include <sci/svc/rm/sci_rm_api.h>
#include <sci/sci_rpc.h>
#include <stdlib.h>
#include "sci_rm_rpc.h"
/* Local Defines */
/* Local Types */
/* Local Functions */
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
sc_bool_t isolated, sc_bool_t restricted,
sc_bool_t grant, sc_bool_t coherent)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_ALLOC;
RPC_U8(&msg, 0U) = (uint8_t)secure;
RPC_U8(&msg, 1U) = (uint8_t)isolated;
RPC_U8(&msg, 2U) = (uint8_t)restricted;
RPC_U8(&msg, 3U) = (uint8_t)grant;
RPC_U8(&msg, 4U) = (uint8_t)coherent;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (pt != NULL) {
*pt = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_CONFIDENTIAL;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_U8(&msg, 1U) = (uint8_t)retro;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_FREE;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_DID;
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_rm_did_t) result;
}
sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_STATIC;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_U8(&msg, 1U) = (uint8_t)did;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_LOCK;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_PARTITION;
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (pt != NULL) {
*pt = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PARENT;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_U8(&msg, 1U) = (uint8_t)pt_parent;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
sc_bool_t move_rsrc, sc_bool_t move_pads)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MOVE_ALL;
RPC_U8(&msg, 0U) = (uint8_t)pt_src;
RPC_U8(&msg, 1U) = (uint8_t)pt_dst;
RPC_U8(&msg, 2U) = (uint8_t)move_rsrc;
RPC_U8(&msg, 3U) = (uint8_t)move_pads;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_RESOURCE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)pt;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
sc_rsrc_t resource_lst, sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_RESOURCE_MOVABLE;
RPC_U16(&msg, 0U) = (uint16_t)resource_fst;
RPC_U16(&msg, 2U) = (uint16_t)resource_lst;
RPC_U8(&msg, 4U) = (uint8_t)movable;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)movable;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_spa_t sa, sc_rm_spa_t pa,
sc_bool_t smmu_bypass)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_ATTRIBUTES;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)sa;
RPC_U8(&msg, 3U) = (uint8_t)pa;
RPC_U8(&msg, 4U) = (uint8_t)smmu_bypass;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_SID;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U16(&msg, 2U) = (uint16_t)sid;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_pt_t pt, sc_rm_perm_t perm)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_U8(&msg, 2U) = (uint8_t)pt;
RPC_U8(&msg, 3U) = (uint8_t)perm;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_OWNED;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_bool_t)result;
}
sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_MASTER;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_bool_t)result;
}
sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_PERIPHERAL;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_bool_t)result;
}
sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_sid_t *sid)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_RESOURCE_INFO;
RPC_U16(&msg, 0U) = (uint16_t)resource;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (sid != NULL) {
*sid = RPC_U16(&msg, 0U);
}
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
sc_faddr_t addr_start, sc_faddr_t addr_end)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_ALLOC;
RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
RPC_U32(&msg, 4U) = (uint32_t)addr_start;
RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
RPC_U32(&msg, 12U) = (uint32_t)addr_end;
RPC_SIZE(&msg) = 5U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mr != NULL) {
*mr = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
sc_faddr_t addr_end)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_SPLIT;
RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
RPC_U32(&msg, 4U) = (uint32_t)addr_start;
RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
RPC_U32(&msg, 12U) = (uint32_t)addr_end;
RPC_U8(&msg, 16U) = (uint8_t)mr;
RPC_SIZE(&msg) = 6U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mr_ret != NULL) {
*mr_ret = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_FREE;
RPC_U8(&msg, 0U) = (uint8_t)mr;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
sc_faddr_t addr_start, sc_faddr_t addr_end)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_FIND_MEMREG;
RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
RPC_U32(&msg, 4U) = (uint32_t)addr_start;
RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
RPC_U32(&msg, 12U) = (uint32_t)addr_end;
RPC_SIZE(&msg) = 5U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mr != NULL) {
*mr = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_MEMREG;
RPC_U8(&msg, 0U) = (uint8_t)pt;
RPC_U8(&msg, 1U) = (uint8_t)mr;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_rm_pt_t pt, sc_rm_perm_t perm)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MEMREG_PERMISSIONS;
RPC_U8(&msg, 0U) = (uint8_t)mr;
RPC_U8(&msg, 1U) = (uint8_t)pt;
RPC_U8(&msg, 2U) = (uint8_t)perm;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_MEMREG_OWNED;
RPC_U8(&msg, 0U) = (uint8_t)mr;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_bool_t)result;
}
sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_faddr_t *addr_start, sc_faddr_t *addr_end)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_MEMREG_INFO;
RPC_U8(&msg, 0U) = (uint8_t)mr;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (addr_start != NULL) {
*addr_start =
((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U);
}
if (addr_end != NULL) {
*addr_end =
((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U);
}
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_PAD;
RPC_U16(&msg, 0U) = (uint16_t)pad;
RPC_U8(&msg, 2U) = (uint8_t)pt;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
sc_pad_t pad_lst, sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PAD_MOVABLE;
RPC_U16(&msg, 0U) = (uint16_t)pad_fst;
RPC_U16(&msg, 2U) = (uint16_t)pad_lst;
RPC_U8(&msg, 4U) = (uint8_t)movable;
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_PAD_OWNED;
RPC_U8(&msg, 0U) = (uint8_t)pad;
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_bool_t)result;
}
void sc_rm_dump(sc_ipc_t ipc)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_DUMP;
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
return;
}
/**@}*/
plat/imx/common/sci/svc/rm/sci_rm_rpc.h 0 → 100644
View file @ ff2743e5
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* Header file for the RM RPC implementation.
*
* @addtogroup RM_SVC
* @{
*/
#ifndef SC_RM_RPC_H
#define SC_RM_RPC_H
/* Includes */
/* Defines */
/*!
* @name Defines for RPC RM function calls
*/
/*@{*/
#define RM_FUNC_UNKNOWN 0 /* Unknown function */
#define RM_FUNC_PARTITION_ALLOC 1U /* Index for rm_partition_alloc() RPC call */
#define RM_FUNC_SET_CONFIDENTIAL 31U /* Index for rm_set_confidential() RPC call */
#define RM_FUNC_PARTITION_FREE 2U /* Index for rm_partition_free() RPC call */
#define RM_FUNC_GET_DID 26U /* Index for rm_get_did() RPC call */
#define RM_FUNC_PARTITION_STATIC 3U /* Index for rm_partition_static() RPC call */
#define RM_FUNC_PARTITION_LOCK 4U /* Index for rm_partition_lock() RPC call */
#define RM_FUNC_GET_PARTITION 5U /* Index for rm_get_partition() RPC call */
#define RM_FUNC_SET_PARENT 6U /* Index for rm_set_parent() RPC call */
#define RM_FUNC_MOVE_ALL 7U /* Index for rm_move_all() RPC call */
#define RM_FUNC_ASSIGN_RESOURCE 8U /* Index for rm_assign_resource() RPC call */
#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /* Index for rm_set_resource_movable() RPC call */
#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /* Index for rm_set_subsys_rsrc_movable() RPC call */
#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /* Index for rm_set_master_attributes() RPC call */
#define RM_FUNC_SET_MASTER_SID 11U /* Index for rm_set_master_sid() RPC call */
#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /* Index for rm_set_peripheral_permissions() RPC call */
#define RM_FUNC_IS_RESOURCE_OWNED 13U /* Index for rm_is_resource_owned() RPC call */
#define RM_FUNC_IS_RESOURCE_MASTER 14U /* Index for rm_is_resource_master() RPC call */
#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /* Index for rm_is_resource_peripheral() RPC call */
#define RM_FUNC_GET_RESOURCE_INFO 16U /* Index for rm_get_resource_info() RPC call */
#define RM_FUNC_MEMREG_ALLOC 17U /* Index for rm_memreg_alloc() RPC call */
#define RM_FUNC_MEMREG_SPLIT 29U /* Index for rm_memreg_split() RPC call */
#define RM_FUNC_MEMREG_FREE 18U /* Index for rm_memreg_free() RPC call */
#define RM_FUNC_FIND_MEMREG 30U /* Index for rm_find_memreg() RPC call */
#define RM_FUNC_ASSIGN_MEMREG 19U /* Index for rm_assign_memreg() RPC call */
#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /* Index for rm_set_memreg_permissions() RPC call */
#define RM_FUNC_IS_MEMREG_OWNED 21U /* Index for rm_is_memreg_owned() RPC call */
#define RM_FUNC_GET_MEMREG_INFO 22U /* Index for rm_get_memreg_info() RPC call */
#define RM_FUNC_ASSIGN_PAD 23U /* Index for rm_assign_pad() RPC call */
#define RM_FUNC_SET_PAD_MOVABLE 24U /* Index for rm_set_pad_movable() RPC call */
#define RM_FUNC_IS_PAD_OWNED 25U /* Index for rm_is_pad_owned() RPC call */
#define RM_FUNC_DUMP 27U /* Index for rm_dump() RPC call */
/*@}*/
/* Types */
/* Functions */
/*!
* This function dispatches an incoming RM RPC request.
*
* @param[in] caller_pt caller partition
* @param[in] msg pointer to RPC message
*/
void rm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an RM RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void rm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* SC_RM_RPC_H */
/**@}*/
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