- 28 Jun, 2021 4 commits
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Usama Arif authored
Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I8d3342315a46c78b4c41582ec114f0364a194316
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Usama Arif authored
"arm,psci" expects the FIDs for cpu-on, cpu-off and cpu-suspend, which arent present in the device tree, so remove it from psci compatible. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: Icd1ce8ec7fd3f270925e4b3d5d0187088ffe4ba5
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Usama Arif authored
The MHUv2 driver has been merged upstream, and it has a different dts format compared to what was previously used. This patch aligns with the upstream driver. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: Ic963c21c1475d301c3a75686718e6e17841831c3
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Arunachalam Ganapathy authored
As FF-A driver probes OP-TEE SP dynamically, these entries are no more required. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Ica091722a7fad13e02662b9b2cd11ca1879b9f80
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- 22 Jun, 2021 1 commit
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Anders Dellien authored
We will maintain the kernel command line here instead of in U-Boot. Signed-off-by: Anders Dellien <anders.dellien@arm.com> Change-Id: I6011306cbaf47717c061f542e180005281695516
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- 30 Apr, 2021 1 commit
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Usama Arif authored
This allows the the Matterhorn ELP Arm core to operate at its designated OPP. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I7ccef0cfd079d630c3cfe7874590bf42789a1dca
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- 14 Apr, 2021 1 commit
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Usama Arif authored
The number of ITS have changed from 4 to 1, resulting in GICR base address change. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
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- 09 Feb, 2021 1 commit
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Usama Arif authored
This allows Matterhorn cores to operate at their optimal OPPs. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I2e1b784da10154a1f1f65dd0e3a39213e7683116
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- 03 Feb, 2021 1 commit
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Avinash Mehta authored
Increase the core count and add respective entries in DTS. Add Klein assembly file to cpu sources for core initialization. Add SCMI entries for cores. Signed-off-by: Avinash Mehta <avinash.mehta@arm.com> Change-Id: I14dc1d87df6dcc8d560ade833ce1f92507054747
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- 27 Jan, 2021 1 commit
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Nikos Nikoleris authored
The value of stdout-path is a string and as a result, we can't use a label as a reference to the serial0 node. This change fixes the stdout-path property for N1SDP, Morello and TC0 by pointing to the right alias. Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Change-Id: I3d403389a424569be56327fab4140fec06f96d37
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- 14 Dec, 2020 2 commits
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Arunachalam Ganapathy authored
Add reserved-memory region for OP-TEE and mark as no-map. This memory region is used by OP-TEE as non-secure shared RAM. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I5a22999a8c5550024d0f47e848d35924017df245
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Arunachalam Ganapathy authored
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2 - create SPMC manifest file with OP-TEE as SP - add support for ARM_SPMC_MANIFEST_DTS build option - add optee entry with ffa as method in tc0.dts Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Ia9b5c22c6f605d3886914bbac8ac45e8365671cb
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- 20 Oct, 2020 1 commit
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Arunachalam Ganapathy authored
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1 - Add TC0_NS_DRAM1 base and mapping - Reserve memory region in tc0.dts Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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- 22 Sep, 2020 1 commit
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Usama Arif authored
This is as part of the architecture change in TC0. Change-Id: I470241f67938e7998941d26f0e8bc05073234152 Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 08 Sep, 2020 1 commit
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Avinash Mehta authored
This change replaces hdlcd with DPU in dts file for TC0 Change-Id: If25dfd3ddffc07279ab487f65e1bb82b27a26604 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
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- 27 Aug, 2020 2 commits
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Usama Arif authored
This includes both cpu and cluster sleep parameters. Change-Id: I6a9e90b88508d6d2acd2538007cbbdd1cf976442 Signed-off-by: Usama Arif <usama.arif@arm.com>
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Usama Arif authored
The pl180 mmc uses 3.3V fixed regulator and vexpress sysreg for card detection and write protect. Change-Id: I2513cfcb97217e282a081a700f3a9f723e8207ff Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 27 May, 2020 1 commit
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Usama Arif authored
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
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