- 24 May, 2016 1 commit
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Stefan Krsmanovic authored
Access to APU_PWRCTRL register is protected during suspend/wakeup pocedure in order to save valid state. If more than one CPU is accessing this register it can be left in corrupted state during read-modify-write process. Signed-off-by:
Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by:
Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 06 Apr, 2016 1 commit
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Soren Brinkmann authored
The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by:
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