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  1. 20 Jun, 2019 1 commit
  3. 03 Apr, 2019 1 commit
  5. 01 Mar, 2019 1 commit
    • Varun Wadekar's avatar
      Tegra: dummy support for the io_storage backend · 8d56e24b
      Varun Wadekar authored 
      

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8d56e24b
  7. 05 Feb, 2019 3 commits
  9. 31 Jan, 2019 14 commits
  11. 23 Jan, 2019 15 commits
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: remove usage of ENABLE_SMMU_DEVICE config · fc5adf7d
      Varun Wadekar authored 
      

This patch removes the usage of this platform config, as it is always
enabled by all the supported platforms.

Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      fc5adf7d
    • Dilan Lee's avatar
      Tegra: add 'late' platform setup handler · 3e1923d9
      Dilan Lee authored 
      

This patch adds a platform setup handler that gets called after
the MMU is enabled. Platforms wanting to make use of this handler
should declare 'plat_late_platform_setup' handler in their platform
files, to override the default weakly defined handler.

Change-Id: Ibc97a2e5a24608ddea856d0bd543a9d5876f604c
Signed-off-by: default avatarDilan Lee <dilee@nvidia.com>
      3e1923d9
    • Varun Wadekar's avatar
      Tegra: spe: shared console for Tegra platforms · dd20f5b3
      Varun Wadekar authored 
      

There are Tegra platforms which have limited UART ports and so
all the components have to share the console. The SPE helps out
by collecting all the logs in such cases and prints them on the
shared UART port.

This patch adds a driver to communicate with the SPE driver, which
in turn provides the console.

Change-Id: Ie750520b936b8bed0ab1d876f03fc0a3490a85a3
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      dd20f5b3
    • Varun Wadekar's avatar
      Tegra: console driver compilation from platform makefiles · 4cba6985
      Varun Wadekar authored 
      

This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms to include consoles of their choice.

Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4cba6985
    • Varun Wadekar's avatar
      Tegra: smmu: change exit criteria for context size calculation · 2ad1bddc
      Varun Wadekar authored 
      

Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF.
This patch changes the search criteria, to look for this marker, to
calculate the size of the saved context.

Change-Id: I15d91945ecb78267f91c45f37985dbb2327ca3ae
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2ad1bddc
    • Steven Kao's avatar
      Tegra: memctrl_v2: platform handler for TZDRAM setup · c63ec263
      Steven Kao authored 
      

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform custom steps during TZDRAM setup.

Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      c63ec263
    • Varun Wadekar's avatar
      Tegra: bpmp: return error if BPMP init fails · d7be5e2e
      Varun Wadekar authored 
      

This patch returns error if BPMP initialization fails. The platform
code marks the cluster as "runnning" since we wont be able to get
it into the low power state without BPMP.

Change-Id: I86f51d478626240bb7b4ccede8907674290c5dc1
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d7be5e2e
    • Steven Kao's avatar
      Tegra: rename secure scratch register macros · 601a8e54
      Steven Kao authored 
      

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
      keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      601a8e54
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: platform handler for TZDRAM settings · d5bd0de6
      Varun Wadekar authored 
      

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.

Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d5bd0de6
    • Varun Wadekar's avatar
      Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware · 26e2b93a
      Varun Wadekar authored 
      

This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
disable requests, module resets among other things.

MRQ is short for Message ReQuest. This is the general purpose, multi channel
messaging protocol that is widely used to communicate with BPMP. This is further
divided into a common high level protocol and a peer-specific low level protocol.
The higher level protocol specifies the peer identification, channel definition
and allocation, message structure, message semantics and message dispatch process
whereas the lower level protocol defines actual message transfer implementation
details. Currently, BPMP supports two lower level protocols - Token Mail Operations
(TMO), IVC Mail Operations (IMO).

This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
Communication) protocol which is a lockless, shared memory messaging queue management
protocol.

The IVC peer is expected to perform the following as part of establishing a connection
with BPMP.

1. Initialize the channels with tegra_ivc_init() or its equivalent.
2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
   BPMP is notified via the doorbell.
3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
   0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
   non zero.

The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
future, more hardware blocks would be supported.

Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      26e2b93a
    • Varun Wadekar's avatar
      Tegra: call 'early_init' handler earlier during boot · 01da3bd2
      Varun Wadekar authored 
      

This patch calls the 'early_init' handler earlier during boot. This
allows the platforms using Tegra186 onwards to init the BPMP interface
earlier.

Change-Id: I0d540df39de7864ce9051ebe11eca5432c462ebf
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      01da3bd2
    • Steven Kao's avatar
      Tegra: memctrl_v2: allow CPU accesses to TZRAM · d6306d14
      Steven Kao authored 
      

This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.

Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      d6306d14
    • Anthony Zhou's avatar
      Tegra: lib: debug: fix MISRA violation Rule 21.6 · 91196b02
      Anthony Zhou authored 
      

MISRA Rule 21.6, The standard library input/output functions
shall not be used.

This patch removes headers that are not really needed.

Change-Id: I746138ce7ee95d7ca985d020f89b2738d997a7a2
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      91196b02
    • Harvey Hsieh's avatar
      Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH · b886c7c5
      Harvey Hsieh authored 
      

This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exiting System Suspend.

Change-Id: Id76175c2a7d931227589468511365599e2908411
Signed-off-by: default avatarHarvey Hsieh <hhsieh@nvidia.com>
      b886c7c5
    • Puneet Saxena's avatar
      Tegra: memctrl_v2: platform handlers to program MSS · ab2eb455
      Puneet Saxena authored 
      

Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.

Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b
Signed-off-by: default avatarPuneet Saxena <puneets@nvidia.com>
Signed-off-by: default avatarKrishna Reddy <vdumpa@nvidia.com>
      ab2eb455
  13. 18 Jan, 2019 5 commits