- 04 Dec, 2015 1 commit
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Varun Wadekar authored
This patch modifies the Tegra port to support the new platform APIs so that we can disable the compat layer. This includes modifications to the power management and platform topology code. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 25 Nov, 2015 1 commit
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Varun Wadekar authored
This patch renames the tegra_fc_cpu_idle() function to a more appropriate tegra_fc_cpu_powerdn() to better reflect its usage. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 12 Aug, 2015 1 commit
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Varun Wadekar authored
This patch fixes the following macros for Tegra SoCs. * PLATFORM_CORE_COUNT: PLATFORM_CLUSTER_COUNT * PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_NUM_AFFS: PLATFORM_CORE_COUNT + PLATFORM_CLUSTER_COUNT + 1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 31 Jul, 2015 1 commit
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Varun Wadekar authored
This patch removes the bootargs pointer from the platform params structure. Instead the bootargs are passed by the BL2 in the bl32_ep_info struct which is a part of the EL3 params struct. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 27 Jul, 2015 1 commit
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Varun Wadekar authored
The Memory Select Switch Controller routes any CPU transactions to the appropriate slave depending on the transaction address. During system suspend, it loses all config settings and hence the CPU has to restore them during resume. This patch restores the controller's settings for enabling WRAP to INCR burst type conversions on the master ports, for any incoming requests from the AXI slave ports. Tested by performing multiple system suspend cycles. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 24 Jul, 2015 2 commits
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Varun Wadekar authored
This patch implements support for T132 (Denver CPU) based Tegra platforms. The following features have been added: * SiP calls to switch T132 CPU's AARCH mode * Complete PSCI support, including 'System Suspend' * Platform specific MMIO settings * Locking of CPU vector registers Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The validate_power_state() handler checks the power_state for a valid afflvl and state id. Although the afflvl check is common, the state ids are implementation defined. This patch moves the handler to the tegra/soc folder to allow each SoC to validate the power_state for supported parameters. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 17 Jul, 2015 1 commit
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Varun Wadekar authored
This patch introduces the backend required for implementing the delay timer API. Tegra has an on-chip free flowing us timer which can be used as the delay timer. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 06 Jul, 2015 1 commit
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Varun Wadekar authored
This patch implements the get_sys_suspend_power_state() handler required by the PSCI SYSTEM_SUSPEND API. The intent of this handler is to return the appropriate State-ID field which can be utilized in `affinst_suspend()` to suspend to system affinity level. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 12 Jun, 2015 1 commit
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Varun Wadekar authored
This patch adds support to reserve a memory carveout region in the DRAM on Tegra SoCs. The memory controller provides specific registers to specify the aperture's base and size. This aperture can also be changed dynamically in order to re-size the memory available for DRM video playback. In case of the new aperture not overlapping the previous one, the previous aperture has to be cleared before setting up the new one. This means we do not "leak" any video data to the NS world. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 11 Jun, 2015 1 commit
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Varun Wadekar authored
This patch adds support to run a Trusted OS during boot time. The previous stage bootloader passes the entry point information in the 'bl32_ep_info' structure, which is passed over to the SPD. The build system expects the dispatcher to be passed as an input parameter using the 'SPD=<dispatcher>' option. The Tegra docs have also been updated with this information. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 29 May, 2015 1 commit
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Varun Wadekar authored
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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