1. 04 Dec, 2015 1 commit
  2. 25 Nov, 2015 1 commit
  3. 12 Aug, 2015 1 commit
  4. 31 Jul, 2015 1 commit
  5. 27 Jul, 2015 1 commit
    • Varun Wadekar's avatar
      Tegra210: enable WRAP to INCR burst type conversions · 42ca2d86
      Varun Wadekar authored
      
      
      The Memory Select Switch Controller routes any CPU transactions to
      the appropriate slave depending on the transaction address. During
      system suspend, it loses all config settings and hence the CPU has
      to restore them during resume.
      
      This patch restores the controller's settings for enabling WRAP to
      INCR burst type conversions on the master ports, for any incoming
      requests from the AXI slave ports.
      
      Tested by performing multiple system suspend cycles.
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      42ca2d86
  6. 24 Jul, 2015 2 commits
  7. 17 Jul, 2015 1 commit
  8. 06 Jul, 2015 1 commit
  9. 12 Jun, 2015 1 commit
    • Varun Wadekar's avatar
      Reserve a Video Memory aperture in DRAM memory · 9a964510
      Varun Wadekar authored
      
      
      This patch adds support to reserve a memory carveout region in the
      DRAM on Tegra SoCs. The memory controller provides specific registers
      to specify the aperture's base and size. This aperture can also be
      changed dynamically in order to re-size the memory available for
      DRM video playback. In case of the new aperture not overlapping
      the previous one, the previous aperture has to be cleared before
      setting up the new one. This means we do not "leak" any video data
      to the NS world.
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      9a964510
  10. 11 Jun, 2015 1 commit
    • Varun Wadekar's avatar
      Boot Trusted OS' on Tegra SoCs · dc7fdad2
      Varun Wadekar authored
      
      
      This patch adds support to run a Trusted OS during boot time. The
      previous stage bootloader passes the entry point information in
      the 'bl32_ep_info' structure, which is passed over to the SPD.
      
      The build system expects the dispatcher to be passed as an input
      parameter using the 'SPD=<dispatcher>' option. The Tegra docs have
      also been updated with this information.
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      dc7fdad2
  11. 29 May, 2015 1 commit
    • Varun Wadekar's avatar
      Support for NVIDIA's Tegra T210 SoCs · 08438e24
      Varun Wadekar authored
      
      
      T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
      ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
      at a given point in time.
      
      This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
      also adds support to boot secondary CPUs, enter/exit core power states for
      all CPUs in the slow/fast clusters. The support to switch between clusters
      is still not available in this patch and would be available later.
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      08438e24