1. 27 May, 2014 1 commit
    • Dan Handley's avatar
      Further renames of platform porting functions · 9865ac15
      Dan Handley authored
      Rename the ic_* platform porting functions to plat_ic_* to be
      consistent with the other functions in platform.h. Also rename
      bl31_get_next_image_info() to bl31_plat_get_next_image_ep_info()
      and remove the duplicate declaration in bl31.h.
      
      Change-Id: I4851842069d3cff14c0a468daacc0a891a7ede84
      9865ac15
  2. 23 May, 2014 1 commit
    • Dan Handley's avatar
      Split platform.h into separate headers · 5f0cdb05
      Dan Handley authored
      Previously, platform.h contained many declarations and definitions
      used for different purposes. This file has been split so that:
      
      * Platform definitions used by common code that must be defined
        by the platform are now in platform_def.h. The exact include
        path is exported through $PLAT_INCLUDES in the platform makefile.
      
      * Platform definitions specific to the FVP platform are now in
        /plat/fvp/fvp_def.h.
      
      * Platform API declarations specific to the FVP platform are now
        in /plat/fvp/fvp_private.h.
      
      * The remaining platform API declarations that must be ported by
        each platform are still in platform.h but this file has been
        moved to /include/plat/common since this can be shared by all
        platforms.
      
      Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a
      5f0cdb05
  3. 22 May, 2014 1 commit
    • Achin Gupta's avatar
      Introduce interrupt handling framework in BL3-1 · dce74b89
      Achin Gupta authored
      This patch adds a common handler for FIQ and IRQ exceptions in the
      BL3-1 runtime exception vector table. This function determines the
      interrupt type and calls its handler. A crash is reported if an
      inconsistency in the interrupt management framework is detected. In
      the event of a spurious interrupt, execution resumes from the
      instruction where the interrupt was generated.
      
      This patch also removes 'cm_macros.S' as its contents have been moved
      to 'runtime_exceptions.S'
      
      Change-Id: I3c85ecf8eaf43a3fac429b119ed0bd706d2e2093
      dce74b89
  4. 16 May, 2014 1 commit
    • Soby Mathew's avatar
      Rework BL3-1 unhandled exception handling and reporting · a43d431b
      Soby Mathew authored
      This patch implements the register reporting when unhandled exceptions are
      taken in BL3-1. Unhandled exceptions will result in a dump of registers
      to the console, before halting execution by that CPU. The Crash Stack,
      previously called the Exception Stack, is used for this activity.
      This stack is used to preserve the CPU context and runtime stack
      contents for debugging and analysis.
      
      This also introduces the per_cpu_ptr_cache, referenced by tpidr_el3,
      to provide easy access to some of BL3-1 per-cpu data structures.
      Initially, this is used to provide a pointer to the Crash stack.
      
      panic() now prints the the error file and line number in Debug mode
      and prints the PC value in release mode.
      
      The Exception Stack is renamed to Crash Stack with this patch.
      The original intention of exception stack is no longer valid
      since we intend to support several valid exceptions like IRQ
      and FIQ in the trusted firmware context. This stack is now
      utilized for dumping and reporting the system state when a
      crash happens and hence the rename.
      
      Fixes ARM-software/tf-issues#79 Improve reporting of unhandled exception
      
      Change-Id: I260791dc05536b78547412d147193cdccae7811a
      a43d431b
  5. 08 May, 2014 1 commit
    • Soby Mathew's avatar
      Preserve x19-x29 across world switch for exception handling · c3260f9b
      Soby Mathew authored
      Previously exception handlers in BL3-1, X19-X29 were not saved
      and restored on every SMC/trap into EL3. Instead these registers
      were 'saved as needed' as a side effect of the A64 ABI used by the C
      compiler.
      
      That approach failed when world switching but was not visible
      with the TSP/TSPD code because the TSP is 64-bit, did not
      clobber these registers when running and did not support pre-emption
      by normal world interrupts. These scenarios showed
      that the values in these registers can be passed through a world
      switch, which broke the normal and trusted world assumptions
      about these registers being preserved.
      
      The Ideal solution saves and restores these registers when a
      world switch occurs - but that type of implementation is more complex.
      So this patch always saves and restores these registers on entry and
      exit of EL3.
      
      Fixes ARM-software/tf-issues#141
      
      Change-Id: I9a727167bbc594454e81cf78a97ca899dfb11c27
      c3260f9b
  6. 06 May, 2014 2 commits
    • Dan Handley's avatar
      Reduce deep nesting of header files · 97043ac9
      Dan Handley authored
      Reduce the number of header files included from other header
      files as much as possible without splitting the files. Use forward
      declarations where possible. This allows removal of some unnecessary
      "#ifndef __ASSEMBLY__" statements.
      
      Also, review the .c and .S files for which header files really need
      including and reorder the #include statements alphabetically.
      
      Fixes ARM-software/tf-issues#31
      
      Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
      97043ac9
    • Dan Handley's avatar
      Make use of user/system includes more consistent · 35e98e55
      Dan Handley authored
      Make codebase consistent in its use of #include "" syntax for
      user includes and #include <> syntax for system includes.
      
      Fixes ARM-software/tf-issues#65
      
      Change-Id: If2f7c4885173b1fd05ac2cde5f1c8a07000c7a33
      35e98e55
  7. 15 Apr, 2014 1 commit
    • Andrew Thoelke's avatar
      Allocate single stacks for BL1 and BL2 · 2bf28e62
      Andrew Thoelke authored
      The BL images share common stack management code which provides
      one coherent and one cacheable stack for every CPU. BL1 and BL2
      just execute on the primary CPU during boot and do not require
      the additional CPU stacks. This patch provides separate stack
      support code for UP and MP images, substantially reducing the
      RAM usage for BL1 and BL2 for the FVP platform.
      
      This patch also provides macros for declaring stacks and
      calculating stack base addresses to improve consistency where
      this has to be done in the firmware.
      
      The stack allocation source files are now included via
      platform.mk rather than the common BLx makefiles. This allows
      each platform to select the appropriate MP/UP stack support
      for each BL image.
      
      Each platform makefile must be updated when including this
      commit.
      
      Fixes ARM-software/tf-issues#76
      
      Change-Id: Ia251f61b8148ffa73eae3f3711f57b1ffebfa632
      2bf28e62
  8. 26 Mar, 2014 2 commits
  9. 20 Feb, 2014 1 commit
    • Jeenu Viswambharan's avatar
      Add exception vector guards · a7934d69
      Jeenu Viswambharan authored
      This patch adds guards so that an exception vector exceeding 32
      instructions will generate a compile-time error. This keeps the
      exception handlers in check from spilling over.
      
      Change-Id: I7aa56dd0071a333664e2814c656d3896032046fe
      a7934d69
  10. 17 Feb, 2014 2 commits
    • Jeenu Viswambharan's avatar
      Add support for handling runtime service requests · caa84939
      Jeenu Viswambharan authored
      
      
      This patch uses the reworked exception handling support to handle
      runtime service requests through SMCs following the SMC calling
      convention. This is a giant commit since all the changes are
      inter-related. It does the following:
      
      1. Replace the old exception handling mechanism with the new one
      2. Enforce that SP_EL0 is used C runtime stacks.
      3. Ensures that the cold and warm boot paths use the 'cpu_context'
         structure to program an ERET into the next lower EL.
      4. Ensures that SP_EL3 always points to the next 'cpu_context'
         structure prior to an ERET into the next lower EL
      5. Introduces a PSCI SMC handler which completes the use of PSCI as a
         runtime service
      
      Change-Id: I661797f834c0803d2c674d20f504df1b04c2b852
      Co-authored-by: default avatarAchin Gupta <achin.gupta@arm.com>
      caa84939
    • Achin Gupta's avatar
      Setup VBAR_EL3 incrementally · b739f22a
      Achin Gupta authored
      This patch ensures that VBAR_EL3 points to the simple stack-less
      'early_exceptions' when the C runtime stack is not correctly setup to
      use the more complex 'runtime_exceptions'. It is initialised to
      'runtime_exceptions' once this is done.
      
      This patch also moves all exception vectors into a '.vectors' section
      and modifies linker scripts to place all such sections together. This
      will minimize space wastage from alignment restrictions.
      
      Change-Id: I8c3e596ea3412c8bd582af9e8d622bb1cb2e049d
      b739f22a
  11. 17 Jan, 2014 1 commit
  12. 05 Dec, 2013 3 commits
    • Achin Gupta's avatar
      rework general purpose registers save and restore · 4a826dda
      Achin Gupta authored
      The runtime exception handling assembler code used magic numbers for
      saving and restoring the general purpose register context on stack
      memory. The memory is interpreted as a 'gp_regs' structure and the
      magic numbers are offsets to members of this structure. This patch
      replaces the magic number offsets with constants. It also adds compile
      time assertions to prevent an incorrect assembler view of this
      structure.
      
      Change-Id: Ibf125bfdd62ba3a33e58c5f1d71f8c229720781c
      4a826dda
    • Dan Handley's avatar
      Enable third party contributions · ab2d31ed
      Dan Handley authored
      - Add instructions for contributing to ARM Trusted Firmware.
      
      - Update copyright text in all files to acknowledge contributors.
      
      Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
      ab2d31ed
    • Sandrine Bailleux's avatar
      Various improvements/cleanups on the linker scripts · 8d69a03f
      Sandrine Bailleux authored
        - Check at link-time that bootloader images will fit in memory
          at run time and that they won't overlap each other.
        - Remove text and rodata orphan sections.
        - Define new linker symbols to remove the need for platform setup
          code to know the order of sections.
        - Reduce the size of the raw binary images by cutting some sections
          out of the disk image and allocating them at load time, whenever
          possible.
        - Rework alignment constraints on sections.
        - Remove unused linker symbols.
        - Homogenize linker symbols names across all BLs.
        - Add some comments in the linker scripts.
      
      Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
      8d69a03f
  13. 25 Oct, 2013 1 commit