- 30 Apr, 2021 1 commit
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laurenw-arm authored
Updated the list of supported FVP platforms as per the latest FVP release. Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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- 01 Mar, 2021 1 commit
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Manish V Badarkhe authored
Added GIC600AE FVP model version information. Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 09 Feb, 2021 1 commit
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Manish V Badarkhe authored
Added a build option 'FVP_GICR_REGION_PROTECTION' to make redistributor frame of fused/unused cores as read only. Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 13 Jan, 2021 1 commit
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Aditya Angadi authored
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36 to 11.13 build 10 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab
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- 09 Dec, 2020 1 commit
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Aditya Angadi authored
Updated the list of supported FVP platforms with support for RD-N2 FVP. Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 02 Oct, 2020 1 commit
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Manish V Badarkhe authored
Updated the list of supported FVP platform as per latest FVP platform release. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I45ef79aff147ed598a3a92ab6f6b277f7f70604a
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- 17 Aug, 2020 1 commit
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Madhukar Pappireddy authored
SP804 TIMER is not platform specific, and current code base adds multiple defines to use this driver. Like FVP_USE_SP804_TIMER and FVP_VE_USE_SP804_TIMER. This patch removes platform specific build flag and adds generic flag `USE_SP804_TIMER` to be set to 1 by platform if needed. Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 03 Aug, 2020 1 commit
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Madhukar Pappireddy authored
These broken links were found with the help of this command: $> sphinx-build -M linkcheck . build A sample broken link is reported as follows: (line 80) -local- firmware-design.rst#secure-el1-payloads-and-dispatchers Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 22 Jul, 2020 1 commit
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Vijayenthiran Subramaniam authored
Update SGI-575, RD-E1-Edge and RD-N1-Edge FVP versions to 11.10/36 and add RD-N1-Edge-Dual to the list of supported Arm Fixed Virtual Platforms. Change-Id: I9e7e5662324eeefc80d799ca5341b5bc4dc39cbb Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 21 Jul, 2020 1 commit
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Alexei Fedorov authored
This patch adds the following models FVP_Base_Neoverse-E1x1 FVP_Base_Neoverse-E1x2 FVP_Base_Neoverse-E1x4 to the list of supported FVP platforms. Change-Id: Ib526a2a735f17724af3a874b06bf69b4ca85d0dd Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 09 Jun, 2020 1 commit
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Andre Przywara authored
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time. This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support. Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 15 Apr, 2020 1 commit
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laurenw-arm authored
A small set of misc changes to ensure correctness before the v2.3 release. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I5b4e35b3b46616df0453cecff61f5a414951cd62
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- 27 Feb, 2020 1 commit
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Imre Kis authored
Cortex-A65x4 and Cortex-A65AEx8 is now included in the list of the supported Arm Fixed Virtual Platforms. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: Ibfcaec11bc75549d60455e96858d79b679e71e5e
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- 18 Feb, 2020 1 commit
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Alexei Fedorov authored
When TF-A is built with RESET_TO_BL31=1 option, BL31 is the first image to be run and should have all the memory allocated to it except for the memory reserved for Shared RAM at the start of Trusted SRAM. This patch fixes FVP BL31 load address and its image size for RESET_TO_BL31=1 option. BL31 startup address should be set to 0x400_1000 and its maximum image size to the size of Trusted SRAM minus the first 4KB of shared memory. Loading BL31 at 0x0402_0000 as it is currently stated in '\docs\plat\arm\fvp\index.rst' causes EL3 exception when the image size gets increased (i.e. building with LOG_LEVEL=50) but doesn't exceed 0x3B000 not causing build error. Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 10 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This toolchain provides multiple cross compilers and are publicly available on developer.arm.com We build TF-A in CI using: AArch32 bare-metal target (arm-none-eabi) AArch64 ELF bare-metal target (aarch64-none-elf) Change-Id: I910200174d5bad985504d1af4a1ae5819b524003 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 08 Jan, 2020 1 commit
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Mark Dykes authored
This reverts commit de9bf1d8. Change-Id: Iebb6297ce290a10ee850bf6a9c71e7eb530b085f
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- 03 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This toolchain provides multiple cross compilers and are publicly available on www.developer.arm.com We thoroughly test TF-A in CI using: AArch32 bare-metal target (arm-none-eabi) AArch64 ELF bare-metal target (aarch64-none-elf) Change-Id: I2360a3ac6705c68dca781b85e9894867df255b3e Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 27 Nov, 2019 1 commit
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Paul Beesley authored
The User Guide document has grown organically over time and now covers a wide range of topics, making it difficult to skim read and extract information from. Currently, it covers these topics and maybe a couple more: - Requirements (hardware, tools, libs) - Checking out the repo - Basic build instructions - A comprehensive list of build flags - FIP packaging - Building specifically for Juno - Firmware update images - EL3 payloads - Preloaded BL33 boot flow - Running on FVPs - Running on Juno I have separated these out into a few groups that become new documents. Broadly speaking, build instructions for the tools, for TF-A generally, and for specific scenarios are separated. Content relating to specific platforms (Juno and the FVPs are Arm-specific platforms, essentially) has been moved into the documentation that is specific to those platforms, under docs/plat/arm. Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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