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  1. 16 Jan, 2019 3 commits
  3. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  5. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored 
      

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  7. 22 Aug, 2018 1 commit
  9. 27 Apr, 2018 1 commit
    • Masahiro Yamada's avatar
      types: use int-ll64 for both aarch32 and aarch64 · 0a2d5b43
      Masahiro Yamada authored 
      Since commit 031dbb12

 ("AArch32: Add essential Arch helpers"),
it is difficult to use consistent format strings for printf() family
between aarch32 and aarch64.

For example, uint64_t is defined as 'unsigned long long' for aarch32
and as 'unsigned long' for aarch64.  Likewise, uintptr_t is defined
as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64.

A problem typically arises when you use printf() in common code.

One solution could be, to cast the arguments to a type long enough
for both architectures.  For example, if 'val' is uint64_t type,
like this:

  printf("val = %llx\n", (unsigned long long)val);

Or, somebody may suggest to use a macro provided by <inttypes.h>,
like this:

  printf("val = %" PRIx64 "\n", val);

But, both would make the code ugly.

The solution adopted in Linux kernel is to use the same typedefs for
all architectures.  The fixed integer types in the kernel-space have
been unified into int-ll64, like follows:

    typedef signed char           int8_t;
    typedef unsigned char         uint8_t;

    typedef signed short          int16_t;
    typedef unsigned short        uint16_t;

    typedef signed int            int32_t;
    typedef unsigned int          uint32_t;

    typedef signed long long      int64_t;
    typedef unsigned long long    uint64_t;

[ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ]

This gets along with the codebase shared between 32 bit and 64 bit,
with the data model called ILP32, LP64, respectively.

The width for primitive types is defined as follows:

                   ILP32           LP64
    int            32              32
    long           32              64
    long long      64              64
    pointer        32              64

'long long' is 64 bit for both, so it is used for defining uint64_t.
'long' has the same width as pointer, so for uintptr_t.

We still need an ifdef conditional for (s)size_t.

All 64 bit architectures use "unsigned long" size_t, and most 32 bit
architectures use "unsigned int" size_t.  H8/300, S/390 are known as
exceptions; they use "unsigned long" size_t despite their architecture
is 32 bit.

One idea for simplification might be to define size_t as 'unsigned long'
across architectures, then forbid the use of "%z" string format.
However, this would cause a distortion between size_t and sizeof()
operator.  We have unknowledge about the native type of sizeof(), so
we need a guess of it anyway.  I want the following formula to always
return 1:

  __builtin_types_compatible_p(size_t, typeof(sizeof(int)))

Fortunately, ARM is probably a majority case.  As far as I know, all
32 bit ARM compilers use "unsigned int" size_t.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      0a2d5b43
  11. 21 Sep, 2017 1 commit
    • Antonio Nino Diaz's avatar
      Fix type of `unsigned long` constants · e47ac1fd
      Antonio Nino Diaz authored 
      

The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in
AArch64. This is inconsistent and that's why we avoid using it as per
the Coding Guidelines. This patch changes all `UL` occurrences to `U`
or `ULL` depending on the context so that the size of the constant is
clear.

This problem affected the macro `BIT(nr)`. As long as this macro is used
to fill fields of registers, that's not a problem, since all registers
are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the
macro is used to fill the fields of a 64-bit integer, it won't be able
to set the upper 32 bits in AArch32.

By changing the type of this macro to `unsigned long long` the behaviour
is always the same regardless of the architecture, as this type is
64-bit wide in both cases.

Some Tegra platform files have been modified by this patch.

Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      e47ac1fd
  13. 14 Jul, 2017 1 commit
  15. 15 Jun, 2017 1 commit
    • Anthony Zhou's avatar
      Tegra186: mce: fix MISRA defects · ab712fd8
      Anthony Zhou authored 
      

Main fixes:

* Added explicit casts (e.g. 0U) to integers in order for them to be
  compatible with whatever operation they're used in [Rule 10.1]
* Force operands of an operator to the same type category [Rule 10.4]
* Added curly braces ({}) around if/while statements in order to
  make them compound [Rule 15.6]
* Added parentheses [Rule 12.1]
* Voided non C-library functions whose return types are not used [Rule 17.7]

Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ab712fd8
  17. 14 Jun, 2017 1 commit
  19. 03 May, 2017 1 commit
  21. 01 May, 2017 1 commit
  23. 13 Apr, 2017 2 commits
  25. 07 Apr, 2017 4 commits
  27. 05 Apr, 2017 6 commits
  29. 30 Mar, 2017 4 commits
    • Varun Wadekar's avatar
      Tegra186: mce: read MCE's firmware version on "real" platforms · 524bd090
      Varun Wadekar authored 
      

This patch runs the MCE firmware's version check only if the underlying
platform has the capability to the run the firmware. MCE firmware is not
running on simulation platforms, identified by v0.3 or v0.6, read from the
Tegra Chip ID value.

Change-Id: I3b1788b1ee2a0d4464017bb879ac5792cb7022b8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      524bd090
    • Varun Wadekar's avatar
      Tegra: smmu: disable TCU prefetch for all the 64 contexts · 698f4250
      Varun Wadekar authored 
      

This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.

Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      698f4250
    • Varun Wadekar's avatar
      Tegra186: mce: Uncore Perfmon ARI Programming · c11e0ddf
      Varun Wadekar authored 
      

Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence handles reads and writes to these registers by manipulating
the underlying T186 uncore hardware.

To access an uncore perfmon register, CPU software writes the ARI
request registers to specify

* whether the operation is a read or a write,
* which uncore perfmon register to access,
* the uncore perfmon unit, group, and counter number (if necessary),
* the data to write (if the operation is a write).

It then initiates an ARI request to run the uncore perfmon sequence in
the MCE and reads the resulting value of the uncore perfmon register
and any status information from the ARI response registers.

The NS world's MCE driver issues MCE_CMD_UNCORE_PERFMON_REQ command
for the EL3 layer to start the entire sequence. Once the request
completes, the NS world would receive the command status in the X0
register and the command data in the X1 register.

Change-Id: I20bf2eca2385f7c8baa81e9445617ae711ecceea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c11e0ddf
    • Varun Wadekar's avatar
      Tegra186: mce: add the mce_update_cstate_info() helper function · 87a1df73
      Varun Wadekar authored 
      

This patch adds a helper function to the MCE driver to allow its
clients to issue UPDATE_CSTATE_INFO requests, without having to
setup the CPU context struct.

We introduced a struct to encapsulate the request parameters, that
clients can pass on to the MCE driver. The MCE driver gets the
parameters from the struct and programs the hardware accordingly.

Change-Id: I02bce57506c4ccd90da82127805d6b564375cbf1
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      87a1df73
  31. 27 Mar, 2017 1 commit
  33. 23 Mar, 2017 4 commits
    • Varun Wadekar's avatar
      Tegra186: enable support for simulation environment · abd3a91d
      Varun Wadekar authored 
      

The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/disable - MCE firmware version checking is disabled and limited
Memory Controller settings are enabled

Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      abd3a91d
    • Varun Wadekar's avatar
      Tegra186: check MCE firmware version during boot · 5cb89c56
      Varun Wadekar authored 
      

This patch checks that the system is running with the supported MCE
firmware during boot. In case the firmware version does not match the
interface header version, then the system halts.

Change-Id: Ib82013fd1c1668efd6f0e4f36cd3662d339ac076
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5cb89c56
    • Varun Wadekar's avatar
      Tegra186: mce: enable LATIC for chip verification · 66ec1125
      Varun Wadekar authored 
      

This patch adds a new interface to allow for making an ARI call that
will enable LATIC for the chip verification software harness.

LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are
used for various measurements relevant ot particular locations in
Silicon. They are small counters which can be polled to determine
how fast a particular location in the Silicon is.

Original change by Guy Sotomayor <gsotomayor@nvidia.com>

Change-Id: Ifb49b8863a009d4cdd5d1ba38a23b5374500a4b3
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      66ec1125
    • Varun Wadekar's avatar
      Tegra186: save/restore BL31 context to/from TZDRAM · 68c7de6f
      Varun Wadekar authored 
      

This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we need to copy the entire BL31 code to
TZDRAM before entering the state.

In order to restore the state on exiting system suspend, a new
CPU reset handler is implemented which gets copied to TZDRAM
during boot. TO keep things simple we use this same reset handler
for booting secondary CPUs too.

Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      68c7de6f
  35. 22 Mar, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra186: implement support for System Suspend · 50402b17
      Varun Wadekar authored 
      

This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.

Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50402b17
    • Varun Wadekar's avatar
      Tegra186: smmu: driver for the smmu hardware block · 4122151f
      Varun Wadekar authored 
      

This patch adds a device driver for the SMMU hardware block on
Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on
Tegra186. The driver only supports saving the SMMU settings
before entering system suspend. The MC driver and the NS world
clients take care of programming their own settings.

Change-Id: Iab5a90310ee10f6bc8745451ce50952ab3de7188
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4122151f
  37. 20 Mar, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra186: support for C6/C7 CPU_SUSPEND states · 7afd4637
      Varun Wadekar authored 
      

This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is
an idle state while C7 is a powerdown state.

The MCE block takes care of the entry/exit to/from these core power
states and hence we call the corresponding MCE handler to process
these requests. The NS driver passes the tentative time that the
core is expected to stay in this state as part of the power_state
parameter, which we store in a per-cpu array and pass it to the
MCE block.

Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7afd4637
    • Varun Wadekar's avatar
      Tegra186: mce: driver for the CPU complex power manager block · 7808b06b
      Varun Wadekar authored 
      

The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an
offload engine for BPMP to do voltage related sequencing and for
hardware requests to be handled in a better latency than BPMP-firmware.

There are two interfaces to the MCEs - Abstract Request Interface (ARI)
and the traditional NVGINDEX/NVGDATA interface.

MCE supports various commands which can be used by CPUs - ARM as well
as Denver, for power management and reset functionality. Since the
linux kernel is the master for all these scenarios, each MCE command
can be issued by a corresponding SMC. These SMCs have been moved to
SiP SMC space as they are specific to the Tegra186 SoC.

Change-Id: I67bee83d2289a8ab63bc5556e5744e5043803e51
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7808b06b