- 07 Dec, 2020 2 commits
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Pali Rohár authored
Rather create a temporary copy in $(BUILD_PLAT) and modify only copy. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I256c029106ea6f69faa086fc4e5bee9f68cd257f
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Pali Rohár authored
$(WTMI_IMG) is used only by $(MAKE) subprocess in $(DOIMAGEPATH) directory. So calling truncate on $(WTMI_IMG) after $(MAKE) in $(DOIMAGEPATH) has no effect and can just damage input file for future usage. Therefore remove this truncate call. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I9925c54c5d3d10eadc19825c5565ad4598a739a7
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- 19 Nov, 2020 3 commits
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Pali Rohár authored
Marvell's TF-A fork has SUBVERSION set to devel-18.12.2. The only differences between Marvell's devel-18.12.0 and devel-18.12.2 versions are documentation updates and cherry-picked patches from TF-A upstream repository. So upstream TF-A has already all changes from Marvell's TF-A devel-18.12.2 fork and therefore update SUBVERSION to reflect this state. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ce946a5176a5cbf124acd8037392463d586b072
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Pali Rohár authored
This new target builds boot-image.bin binary as described in documentation. This image does not contain WTMI image and therefore WTP repository is not required for building. Having ability to build just this boot-image.bin binary without full flash-image.bin is useful for A3720 Turris MOX board which does not use Marvell's WTP and a3700_utils. To reduce duplicity between a8k and a3k code, define this new target and also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file marvell_common.mk. For this purpose it is needed to include plat/marvell/marvell.mk file from a3700_common.mk unconditionally (and not only when WTP is defined). Now when common file plat/marvell/marvell.mk does not contain definition for building $(DOIMAGETOOL), it is possible to move its inclusion at the top of the a3700_common.mk file. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280
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Pali Rohár authored
Current binary wtptp/linux/tbb_linux which is specified in $(DOIMAGETOOL) variable points to external pre-compiled Marvell x86_64 ELF linux binary from A3700-utils-marvell WTP repository. It means that currently it is not possible to compile TF-A for A3720 on other host platform then linux x86_64. Part of the A3700-utils-marvell WTP repository is also source code of $(DOIMAGETOOL) TBB_Linux tool. This change adds support for building $(DOIMAGETOOL) also for a3k platform. After running $(MAKE) at appropriate subdirectory of A3700-utils-marvell WTP repository, compiled TBB_linux tool will appear in WTP subdirectory wtptp/src/TBB_Linux/release/. So update also $(DOIMAGETOOL) variable to point to the correct location where TBB_linux was built. To build TBB_linux it is required to compile external Crypto++ library which is available at: https://github.com/weidai11/cryptopp.git User needs to set CRYPTOPP_PATH option to specify path to that library. After this change it is now possible to build whole firmware for A3720 platform without requirement to use pre-compiled/proprietary x86_64 executable binaries from Marvell. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I6f26bd4356778a2f8f730a223067a2e550e6c8e0
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- 21 Oct, 2020 1 commit
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Pali Rohár authored
Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6
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- 19 Oct, 2020 1 commit
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Pali Rohár authored
Include file plat/marvell/marvell.mk for platform A3700 was included two times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and second time from common file plat/marvell/armada/common/marvell_common.mk. It caused following warning every time was make called: plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean' plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean' Change in this commit removes inclusion of plat/marvell/marvell.mk file in common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform needs this include file, add it also into a80x0 platform specific include file lat/marvell/armada/a8k/common/a8k_common.mk. Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL are already defined, but it defines MARVELL_SECURE_BOOT variable which is needed by plat/marvell/armada/a3k/common/a3700_common.mk. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa
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- 16 Oct, 2020 1 commit
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Pali Rohár authored
For building fip image it is not needed to build target mrvl_flash. This fip image contains only bl2, bl31 and bl33 (u-boot.bin) images and therefore it does not depend on Marvell wtmi and wtp A3700-utils. So remove mrvl_flash dependency for fip target to allow building fip image without need to build mrvl_flash and therefore specify and provide Marvell wmi and wtp A3700-utils. This changes fixes compilation of fip image for A3700 platform by command: make CROSS_COMPILE=aarch64-linux-gnu- BL33=/path/u-boot/u-boot.bin \ DEBUG=0 LOG_LEVEL=0 USE_COHERENT_MEM=0 PLAT=a3700 fip Marvell boot image can be still build by 'mrvl_flash' target. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iba9a9da5be6fd1da23407fc2d490aedcb1a292c9
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- 15 Oct, 2020 1 commit
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Pali Rohár authored
plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it Some of targets (e.g. mrvl_flash) depends on WTP build option. Other targets (e.g. fip) can be build also without WTP build option as they do not depend on it. This change put all A3720 variables and targets which depends on WTP into conditional if-endif section, so they are not defined when user has not supplied WTP build option. Target mrvl_flash is defined also when WTP was not specified and in this case it just print error message to help user. Variables which do not depend on WTP are moved to the top of a3700_common.mk file. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Idb3892233586a0afca3e0e6564279641d2e4b960
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- 09 Oct, 2020 1 commit
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Jimmy Brisson authored
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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- 04 Oct, 2020 5 commits
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Konstantin Porotchkin authored
Add *.bin extension to UART recovery images archive name. Such naming will cause the UART recovery images to be copied to the Buildroot output folder upon flash image build. Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Marvell uses RAM address 0x0 for loading BL33 stage images. When ATF is built with DEBUG=1, its IO subsystem fails on assert checking the destination RAM address != 0. This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform allowing to bypass the above check in debug mode. Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
The polarity inversion for USB was not tested due to lack of hw design which requires it. Currently all supported boards doesn't require USB phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Enable the option for the ones that need it. Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
The cp110 comphy has ability to invert RX and/or TX polarity. Polarity depends on board design. Currently all supported boards doesn't require SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Stefan Chulski authored
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading CNTVAL reflects the global system counter value in binary format. Due to this erratum, the CNTVAL value presented to the processor may be incorrect for several clock cycles. Workaround: Override the default value of AP Register Device General control 20 [19:16] and AP Register Device General Control 21 [11:8] to the value of 0x3. Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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- 04 Aug, 2020 1 commit
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Grant Likely authored
If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
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- 30 Jul, 2020 6 commits
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Grzegorz Jaszczyk authored
CN-9130 has single CP0 inside the package and 2 additional one from MoChi interface. In case of db-9130-modular board the MCI interface is routed to: - on-board CP115 (MCI0) - extension board CP115 (MCI1) The board is based on DIMM DDR. The 9130 has up to 3CP, and decoding windows looks like below: (free for further use) .----------. 0xf800 0000 | CP2 CFG | '----------' 0xf600 0000 | CP1 CFG | '----------' 0xf400 0000 | CP0 CFG | '----------' 0xf200 0000 | AP CFG | '----------' 0xf000 0000 (free for further use) .----------. 0xec00 0000 | SPI | | MEM_MAP | (Currently not opened) '----------' 0xe800 0000 | PEX2_CP2 | '----------' 0xe700 0000 | PEX1_CP2 | '----------' 0xe600 0000 | PEX0-CP2 | '----------' .----------. 0xe500 0000 | PEX2_CP1 | '----------' 0xe400 0000 | PEX1_CP1 | '----------' 0xe300 0000 | PEX0-CP1 | '----------' .----------. 0xe200 0000 | PEX2-CP0 | '----------' 0xe100 0000 | PEX1-CP0 | '----------' 0xe000 0000 | PEX0-CP0 | | 512MB | '----------' 0xc000 0000 Change-Id: Ia8eee4f96c1043753f74f9da437b9f72ce2d6eb0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Alex Evraev authored
As the preparation for adding the CN913x SoC family support introduce code that enable SVC and the frequency handling specific for the AP807 North Bridge. Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3 Signed-off-by: Alex Evraev <alexev@marvell.com>
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Grzegorz Jaszczyk authored
Update AVS settings and remove unused macros. This is a preparation patch for adding CN913x SoC family support. Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Ben Peled authored
Add CN913x case to bl2_plat_get_cp_count. Fix loading of cp1/2 image. This is a preparation patch for adding CN913x SoC family support. Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9 Signed-off-by: Ben Peled <bpeled@marvell.com>
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Alex Evraev authored
Add support for “AVS reduction” feature at this mode for 7040 Dual Cluster operation mode at CPU=1600MHz Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2 Signed-off-by: Alex Evraev <alexev@marvell.com>
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Moti Buskila authored
the twin-die combined memory device should be treated as X8 device and not as X16 one. This patch is required to re-enable compilation after BLE (mv-ddr-marvell) firmware upgrade. Change-Id: I41257ff2825164ebca85a84bbb8462d7b3447b97 Signed-off-by: Moti Buskila <motib@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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- 10 Jul, 2020 6 commits
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Grzegorz Jaszczyk authored
There is no need to open tree different IO window when there is possibility of having one covering required range. Change-Id: I9feae1fc583df1f7d97d28161cf7601f43513856 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Marcin Wojtas authored
Update missing code releated to the BL32 payload. Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Konstantin Porotchkin authored
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module. It is followed by 4MB of shared memory. Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
Now when mg_conf_cm3 driver is present - move all relevant code there. Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Implement function which will allow to start AP FW. Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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- 03 Jul, 2020 2 commits
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Luka Kovacic authored
Add support for the iEi Puzzle-M801 board that is based on the Marvell Armada 88F8040 SoC. It supports 1 x 288-pin DIMM, DDR4 2400MHz up to 16 GB (ECC). The iEi Puzzle-M801 board is using a custom MCU to handle board power management. The MCU is managing the boards power LEDs, fans and some other periferals. It's using UART for communication. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: I0826ef8bf651b69aad5803184f20930ac7212ef8
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Luka Kovacic authored
Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for determening the path of the system_power.c file. The variable was not updated, when it was deprecated in a8k_common.mk in commit 613bbde0 . Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8
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- 19 Jun, 2020 10 commits
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Konstantin Porotchkin authored
Adjust the latest OP-TEE memory definitions to the newest TF-A baseline. Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell cache_lls driver. Add LLC_SRAM definition to Marvell common makefile - disabled by the default. Add description of LLC_SRAM flag to the build documentation. Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Extend the CCU tables with secure SRAM window in all board setups that uses SoCs based on AP806/AP807 North Bridges Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Marcin Wojtas authored
It is not needed to reserve 64MB for FIP. Limit this to 4MB for both supported Armada SoC families. Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Extract from bigger commit] Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Konstantin Porotchkin authored
- Remove TRUSTED_DRAM_BASE TRUSTED_DRAM_SIZE MARVELL_TRUSTED_SRAM_BASE - Rename PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_* PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_* MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM - Move MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h - Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map - Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM - Add minor style improvents Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Improve patch after rebase] Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Konstantin Porotchkin authored
Make sure the current CCU window is not in use before adding a new address map during MSS BL2 image load preparations. At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is added to MSS BL2 stage initialization, the DDR entry will be destroyed and lead to the system hang. Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Make all LLC-related macros to start with the same prefix Add more LLC control registers definitions This patch is a preparation step for LLC SRAM support Change-Id: I0a4f0fc83e8ef35be93dd239a85f2a9f88d1ab19 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Ben Peled authored
The configuration space of each standalone CP was updated in BL31. Loading FW procedure take places earlier in SCP_BL2. It needs to be done after access to each CP is provided. Moving the proper configuration from BL31 to BL2 solves it. Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea Signed-off-by: Ben Peled <bpeled@marvell.com>
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Konstantin Porotchkin authored
As a preparation to support proper loading the OPTEE OS image, enable the BL32 specific defines in case the SPD is used. On the occasion move two BL32-related macros to marvell_def.h and fix BL32_LIMIT definition. Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Grzegorz Jaszczyk authored
The phy porting layer uses defaults defined in "phy-default-porting-layer.h" when board specific file "phy-porting-layer.h" is not found. Because of the regression the board specific directory was not included, therefore all boards used default parameters. Change-Id: I66e5e6eb8a39cca5aeeb4de6dab2ceddc39c1e31 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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