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  1. 28 Nov, 2019 8 commits
  3. 13 Nov, 2019 6 commits
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  7. 03 Apr, 2019 1 commit
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  11. 05 Feb, 2019 3 commits
  13. 31 Jan, 2019 10 commits
    • Varun Wadekar's avatar
      Tegra: restrict non-secure PMC accesses · a01b0f16
      Varun Wadekar authored 
      

Platforms that do not support bpmp firmware, do not need access
to the PMC block from outside of the CPU complex. The agents
running on the CPU can always access the PMC through the EL3
exception space.

This patch restricts non-secure world access to the PMC block on
such platforms.

Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      a01b0f16
    • Krishna Reddy's avatar
      Tegra186: memctrl: disable stream id writes for MC clients · a7f4e89b
      Krishna Reddy authored 
      

As per the latest recommendations from the hardware team, write access
needs to be disabled for APE, BPMP, NvDec and SCE clients. This patch
disables stream id register writes for these MC clients to implement
those recommendations.

Change-Id: I8887c0f2cc5bc3fc5bba42074810ba5c1d3f121f
Signed-off-by: default avatarKrishna Reddy <vdumpa@nvidia.com>
      a7f4e89b
    • Varun Wadekar's avatar
      Tegra210: toggle ring oscillator across cluster idle · 6a397d1d
      Varun Wadekar authored 
      

This patch toggles the ring oscillator state across cluster idle
as DFLL loses its state. We dont want garbage values being written
to the pmic when we enter cluster idle state, so enable "open loop"
when we enter CC6 and restore the state to "closed loop" on exit.

Change-Id: I56f4649f57bcc651d6c415a6dcdc978e9444c97b
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      6a397d1d
    • kalyani chidambaram's avatar
      Tegra210: clear PMC_DPD registers on resume · da0f4743
      kalyani chidambaram authored 
      

This patch clears the PMC's DPD registers on resuming from System
Suspend, for all Tegra210 platforms that support the sc7entry-fw.

Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305
Signed-off-by: default avatarkalyani chidambaram <kalyanic@nvidia.com>
      da0f4743
    • Varun Wadekar's avatar
      Tegra210: suspend/resume bpmp interface across System Suspend · e275ae7a
      Varun Wadekar authored 
      

The BPMP firmware takes some time to initialise its state on exiting
System Suspend state. The CPU needs to synchronize with the BPMP during
this process to avoid any race conditions. This patch suspends and resumes
the BPMP interface across a System Suspend cycle, to fix this race.

Change-Id: I82a61d12ef3eee267bdd8d4386bed23397fbfd2d
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e275ae7a
    • Varun Wadekar's avatar
      Tegra210: skip past sc7entry-fw signature header · c33473d5
      Varun Wadekar authored 
      

This patch skips past the signature header added to the sc7entry-fw
binary by the previous level bootloader. Currently, the size of
the header is 1KB, so adjust the start address and the binary size
at the time of copy.

Change-Id: Id0494548009749035846d54df417a960c640c8f9
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c33473d5
    • Varun Wadekar's avatar
      Tegra210: move sc7entry-fw inside the TZDRAM fence · 7350277b
      Varun Wadekar authored 
      

This patch uses the sc7entry-fw base/size values to calculate the
TZDRAM fence, so as to move sc7entry-fw inside the TZDRAM fence.

Change-Id: I91aeeeece857076c478cdc4c18a6ad70dc265031
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7350277b
    • kalyani chidambaram's avatar
      Tegra210: SiP handlers to allow PMC access · fdc08e2e
      kalyani chidambaram authored 
      

This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.

Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff
Signed-off-by: default avatarkalyani chidambaram <kalyanic@nvidia.com>
      fdc08e2e
    • Varun Wadekar's avatar
      Tegra210: power off all DMA masters before System Suspend entry · 2d5560f9
      Varun Wadekar authored 
      

This patch puts all the DMA masters in reset before starting the System
Suspend sequence. This helps us make sure that there are no rogue agents
in the system trying to over-write the SC7 Entry Firmware with their own.

Change-Id: I7eb39999d229951e612fbfeb9f86c4efb8f98b5a
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2d5560f9
    • Varun Wadekar's avatar
      Tegra: support for System Suspend using sc7entry-fw binary · 3ca3c27c
      Varun Wadekar authored 
      

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no longer
be supported on Tegra210 platforms and its functionality will be
divided across the CPU and sc7entry-fw.

The sc7entry-fw takes care of performing the hardware sequence required
to enter System Suspend (SC7 power state) from the COP. The CPU is required
to load this firmware to the internal RAM of the COP and start the sequence.
The CPU also make sure that the COP is off after cold boot and is only
powered on when we want to start the actual System Suspend sequence.

The previous bootloader loads the firmware to TZDRAM and passes its base and
size as part of the boot parameters. The EL3 layer is supposed to sanitize
the parameters before touching the firmware blob.

To assist the warmboot code with the PMIC discovery, EL3 is also supposed to
program PMC's scratch register #210, with appropriate values. Without these
settings the warmboot code wont be able to get the device out of System
Suspend.

Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      3ca3c27c