- 08 Jun, 2020 1 commit
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Tien Hock Loh authored
DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by:Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
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- 25 Feb, 2020 2 commits
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by:Andre Przywara <andre.przywara@arm.com>
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Tien Hock, Loh authored
This initializes the EMAC PHY in both Stratix 10 and Agilex, without this, EMAC PHY wouldn't work correctly. Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6 Signed-off-by:Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
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- 03 Feb, 2020 1 commit
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Hadi Asyrafi authored
Platform handoff structure no longer includes boot source selection. Hence, those settings can now be configured through socfpga_plat_def.h. Signed-off-by:
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- 16 Jan, 2020 5 commits
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Hadi Asyrafi authored
Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: -
Hadi Asyrafi authored
Refactored system manager driver to be shared across both intel platform Signed-off-by: -
Hadi Asyrafi authored
Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: -
Hadi Asyrafi authored
Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: -
Hadi Asyrafi authored
Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by:
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- 28 Nov, 2019 4 commits
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Hadi Asyrafi authored
Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: -
Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: -
Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 14 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by:
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 26 Jun, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 21 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Watchdog driver support & enablement during platform setup Signed-off-by:
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- 13 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by:
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- 08 Mar, 2019 2 commits
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Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: -
Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by:
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- 07 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Change map region for device 2 from non-secure to secure Signed-off-by:
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- 13 Feb, 2019 1 commit
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Loh Tien Hock authored
A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by:
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- 04 Feb, 2019 1 commit
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Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by:
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