- 08 Jun, 2020 1 commit
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Manish Pandey authored
As per "include/export/README", TF-A code should never include export headers directly. Instead, it should include a wrapper header that ensures the export header is included in the right manner. "tbbr_img_def_exp.h" is directly included in TF-A code, this patch replaces it with its wrapper header "tbbr_img_def.h". Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I31c1a42e6a7bcac4c396bb17e8548567ecd8147d
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- 30 Apr, 2020 1 commit
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Louis Mayencourt authored
Dynamic configuration properties are fconf properties. Modify the compatible string from "arm,.." to "fconf,.." to reflect this. Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I85eb75cf877c5f4d3feea3936d4c348ca843bc6c
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- 07 Apr, 2020 1 commit
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Vijayenthiran Subramaniam authored
RD-Daniel uses GIC-Clayton as its interrupt controller which is an implementation of GICv4.1 architecture. Hence for RD-Daniel, enable GICv4 extension support. Change-Id: I45ae8c82376f8fe8fc0666306822ae2db74e71b8 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 12 Mar, 2020 1 commit
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Aditya Angadi authored
Add CLCD, HDLCD, PCI and VIRTIO devices as source interfaces for TZC filter unit to enable DMA for these devices. Change-Id: Ifad2e56b18605311936e03cfcccda573cac7e60a Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 19 Feb, 2020 1 commit
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Suyash Pathak authored
A TZC400 controller is placed inline on DRAM channels and regulates the secure and non-secure accesses to both secure and non-secure regions of the DRAM memory. Configure each of the TZC controllers accordingly. Change-Id: I75f6d13591a7fe9e50ce15c793e35a8018041815 Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>
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- 12 Feb, 2020 1 commit
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Louis Mayencourt authored
Change-Id: I011256ca60672a00b711c3f5725211be64bbc2b2 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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- 07 Feb, 2020 1 commit
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Aditya Angadi authored
Add the initial board support for RD-Daniel Config-M platform. Change-Id: I36df16c745bfe4bc817e275ad4722e5de57733cd Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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