1. 23 May, 2014 2 commits
    • Andrew Thoelke's avatar
      Use a vector table for TSP entrypoints · 399fb08f
      Andrew Thoelke authored
      The TSP has a number of entrypoints used by the TSP on different
      occasions. These were provided to the TSPD as a table of function
      pointers, and required the TSPD to read the entry in the table,
      which is in TSP memory, in order to program the exception return
      address.
      
      Ideally, the TSPD has no access to the TSP memory.
      
      This patch changes the table of function pointers into a vector
      table of single instruction entrypoints. This allows the TSPD to
      calculate the entrypoint address instead of read it.
      
      Fixes ARM-software/tf-issues#160
      
      Change-Id: Iec6e055d537ade78a45799fbc6f43765a4725ad3
      399fb08f
    • Soby Mathew's avatar
      Non-Secure Interrupt support during Standard SMC processing in TSP · 239b04fa
      Soby Mathew authored
      Implements support for Non Secure Interrupts preempting the
      Standard SMC call in EL1. Whenever an IRQ is trapped in the
      Secure world we securely handover to the Normal world
      to process the interrupt. The normal world then issues
      "resume" smc call to resume the previous interrupted SMC call.
      Fixes ARM-software/tf-issues#105
      
      Change-Id: I72b760617dee27438754cdfc9fe9bcf4cc024858
      239b04fa
  2. 22 May, 2014 3 commits
    • Achin Gupta's avatar
      Add support for asynchronous FIQ handling in TSP · 57356e90
      Achin Gupta authored
      This patch adds support in the TSP to handle FIQ interrupts that are
      generated when execution is in the TSP. S-EL1 interrupt are handled
      normally and execution resumes at the instruction where the exception
      was originally taken. S-EL3 interrupts i.e. any interrupt not
      recognized by the TSP are handed to the TSPD. Execution resumes
      normally once such an interrupt has been handled at EL3.
      
      Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
      57356e90
    • Achin Gupta's avatar
      Add support for synchronous FIQ handling in TSP · 6cf89021
      Achin Gupta authored
      This patch adds support in the TSP for handling S-EL1 interrupts
      handed over by the TSPD. It includes GIC support in its platform port,
      updates various statistics related to FIQ handling, exports an entry
      point that the TSPD can use to hand over interrupts and defines the
      handover protocol w.r.t what context is the TSP expected to preserve
      and the state in which the entry point is invoked by the TSPD.
      
      Change-Id: I93b22e5a8133400e4da366f5fc862f871038df39
      6cf89021
    • Vikram Kanigiri's avatar
      Rework memory information passing to BL3-x images · 6871c5d3
      Vikram Kanigiri authored
      The issues addressed in this patch are:
      
      1. Remove meminfo_t from the common interfaces in BL3-x,
      expecting that platform code will find a suitable mechanism
      to determine the memory extents in these images and provide
      it to the BL3-x images.
      
      2. Remove meminfo_t and bl31_plat_params_t from all FVP BL3-x
      code as the images use link-time information to determine
      memory extents.
      
      meminfo_t is still used by common interface in BL1/BL2 for
      loading images
      
      Change-Id: I4e825ebf6f515b59d84dc2bdddf6edbf15e2d60f
      6871c5d3
  3. 09 May, 2014 1 commit
    • Sandrine Bailleux's avatar
      fvp: Provide per-EL MMU setup functions · b793e431
      Sandrine Bailleux authored
      Instead of having a single version of the MMU setup functions for all
      bootloader images that can execute either in EL3 or in EL1, provide
      separate functions for EL1 and EL3. Each bootloader image can then
      call the appropriate version of these functions. The aim is to reduce
      the amount of code compiled in each BL image by embedding only what's
      needed (e.g. BL1 to embed only EL3 variants).
      
      Change-Id: Ib86831d5450cf778ae78c9c1f7553fe91274c2fa
      b793e431
  4. 06 May, 2014 1 commit
    • Dan Handley's avatar
      Reduce deep nesting of header files · 97043ac9
      Dan Handley authored
      Reduce the number of header files included from other header
      files as much as possible without splitting the files. Use forward
      declarations where possible. This allows removal of some unnecessary
      "#ifndef __ASSEMBLY__" statements.
      
      Also, review the .c and .S files for which header files really need
      including and reorder the #include statements alphabetically.
      
      Fixes ARM-software/tf-issues#31
      
      Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
      97043ac9
  5. 26 Mar, 2014 1 commit
    • Andrew Thoelke's avatar
      Place assembler functions in separate sections · 0a30cf54
      Andrew Thoelke authored
      This extends the --gc-sections behaviour to the many assembler
      support functions in the firmware images by placing each function
      into its own code section. This is achieved by creating a 'func'
      macro used to declare each function label.
      
      Fixes ARM-software/tf-issues#80
      
      Change-Id: I301937b630add292d2dec6d2561a7fcfa6fec690
      0a30cf54
  6. 20 Feb, 2014 1 commit
    • Achin Gupta's avatar
      Add Test Secure Payload (BL3-2) image · 7c88f3f6
      Achin Gupta authored
      
      
      This patch adds a simple TSP as the BL3-2 image. The secure payload
      executes in S-EL1. It paves the way for the addition of the TSP
      dispatcher runtime service to BL3-1. The TSP and the dispatcher service
      will serve as an example of the runtime firmware's ability to toggle
      execution between the non-secure and secure states in response to SMC
      request from the non-secure state.  The TSP will be replaced by a
      Trusted OS in a real system.
      
      The TSP also exports a set of handlers which should be called in
      response to a PSCI power management event e.g a cpu being suspended or
      turned off. For now it runs out of Secure DRAM on the ARM FVP port and
      will be moved to Secure SRAM later. The default translation table setup
      code assumes that the caller is executing out of secure SRAM. Hence the
      TSP exports its own translation table setup function.
      
      The TSP only services Fast SMCs, is non-reentrant and non-interruptible.
      It does arithmetic operations on two sets of four operands, one set
      supplied by the non-secure client, and the other supplied by the TSP
      dispatcher in EL3. It returns the result according to the Secure Monitor
      Calling convention standard.
      
      This TSP has two functional entry points:
      
      - An initial, one-time entry point through which the TSP is initialized
        and prepares for receiving further requests from secure
        monitor/dispatcher
      
      - A fast SMC service entry point through which the TSP dispatcher
        requests secure services on behalf of the non-secure client
      
      Change-Id: I24377df53399307e2560a025eb2c82ce98ab3931
      Co-authored-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      7c88f3f6