- 22 Feb, 2017 3 commits
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Varun Wadekar authored
The BL2 fills in the UART controller ID to be used as the normal as well as the crash console on Tegra platforms. The controller ID to UART controller base address mapping is handled by each Tegra SoC the base addresses might change across Tegra chips. This patch adds the handler to parse the platform params to get the UART ID for the per-soc handlers. Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch modifies platform_get_core_pos() to use the Cluster ID field as well to calculate the final index value. This helps the system to store CPU data for multi-cluster configurations. Change-Id: I76e35f723f741e995c6c9156e9d61b0b2cdd2709 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch enables the processor retention and L2/CPUECTLR read/write access from the NS world only for Cortex-A57 CPUs on the Tegra SoCs. Change-Id: I9941a67686ea149cb95d80716fa1d03645325445 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 21 Jan, 2016 1 commit
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Juan Castillo authored
The PL011 TRM (ARM DDI 0183G) specifies that the UART must be disabled before any of the control registers are programmed. The PL011 driver included in TF does not disable the UART, so the initialization in BL2 and BL31 is violating this requirement (and potentially in BL1 if the UART is enabled after reset). This patch modifies the initialization function in the PL011 console driver to disable the UART before programming the control registers. Register clobber list and documentation updated. Fixes ARM-software/tf-issues#300 Change-Id: I839b2d681d48b03f821ac53663a6a78e8b30a1a1
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- 04 Dec, 2015 1 commit
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Varun Wadekar authored
This patch modifies the Tegra port to support the new platform APIs so that we can disable the compat layer. This includes modifications to the power management and platform topology code. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 24 Aug, 2015 1 commit
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Varun Wadekar authored
This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers, so that the core waits for 512 generic timer CNTVALUEB ticks before entering retention state, after executing a WFI instruction. This functionality is configurable and can be enabled for platforms by setting the newly defined 'ENABLE_L2_DYNAMIC_RETENTION' and 'ENABLE_CPU_DYNAMIC_RETENTION' flag. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 17 Jul, 2015 1 commit
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Varun Wadekar authored
A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to enable read/write access to the L2 and CPUECTRL registers. T210 is the only platform that needs to enable this config for now. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 29 May, 2015 1 commit
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Varun Wadekar authored
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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