- 08 Jul, 2019 1 commit
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Madhukar Pappireddy authored
Include necessary header file to use ARRAY_SIZE() macro Change-Id: I5b7caccd02c14c598b7944cf4f347606c1e7a8e7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 05 Jul, 2019 1 commit
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Masahiro Yamada authored
The legacy console is gone. Re-add the console support based on the multi-console framework. I am still keeping the putc, getc, and flush callbacks in uniphier_console.S to use plat/common/aarch64/crash_console_helpers.S The console registration code already relies on that C environment has been set up. So, I just filled the struct console fields with the callback pointers, then called console_register() directly. I also re-implemented the init function in C to improve the readability. Removing the custom crash console implementation has one disadvantage; we cannot use the crash console on very early crashes because crash_console_helpers.S works only after the console is registered. I can live with this limitation. Tested on my boards, and confirmed this worked like before. Change-Id: Ieab9c849853ff6c525c15ea894a85944f257db59 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 04 Jul, 2019 2 commits
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Andrew F. Davis authored
These errors are asynchronous and cannot be directly correlated with the exact current running software, so handling them in the same EL is not critical. Handling them in TF-A allows for more platform specific decoding of the implementation defined exception registers Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda
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Jacky Bai authored
CAAM module must be initialized in secure world before it can be used in non-secure world. Change-Id: I042893667ddef99d8b6fc3902847d516d8591996 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 01 Jul, 2019 2 commits
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Soby Mathew authored
Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I2281b3c1b8a0f2caa751c746b7835f998183e0af
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Ambroise Vincent authored
This patch addds multi console interface for ZynqMP platform Change-Id: I508a61412df2b71d04bca6a1139c8f32cbd7dccd Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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- 28 Jun, 2019 3 commits
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Ambroise Vincent authored
Change-Id: Iab788e3e7cb2f83144255c4eb830712fd5cb6240 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: I87818b220568cc34838726b32ddf29ee6cf31ed7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 26 Jun, 2019 5 commits
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Manoj Kumar authored
N1SDP platform supports RDIMMs with ECC capability. To use the ECC capability, the entire DDR memory space has to be zeroed out before enabling the ECC bits in DMC620. Zeroing out several gigabytes of memory from SCP is quite time consuming so functions are added that zeros out the DDR memory from application processor which is much faster compared to SCP. BL33 binary cannot be copied to DDR memory before enabling ECC so this is also done by TF-A from IOFPGA-DDR3 memory to main DDR4 memory after ECC is enabled. Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which the entire DDR space cannot be accessed as DRAM2 starts in base 0x8080000000. So these macros are redefined for all ARM platforms. Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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Hadi Asyrafi authored
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f
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Hadi Asyrafi authored
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0ffccca7ea83bff35c9f149d7054cd610a59ec01
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Hadi Asyrafi authored
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5241ed97697b0280b590b47b9173d102d23f305a
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Hadi Asyrafi authored
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa
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- 22 Jun, 2019 1 commit
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Marek Vasut authored
Now that PFC drivers are cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie594b53558c2bfb8e5d88e5b0354752c17a2487e
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- 20 Jun, 2019 2 commits
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Andreas Färber authored
initilise -> initialise Signed-off-by: Andreas Färber <afaerber@suse.de> Change-Id: Ib129e6bd48623b6565b669bc674208893a2f7668
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Andreas Färber authored
Let bl31_check_ns_address() print the address it doesn't like. Signed-off-by: Andreas Färber <afaerber@suse.de> Change-Id: I29a4fb33c24e9f7464ccd2ea44a4608f5cfe5be6
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- 17 Jun, 2019 8 commits
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Marek Vasut authored
Now that QoS drivers are cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: If61ab2157c30b8f5a6b91d2c56ddbb9098ef99e8
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Yann Gautier authored
Change-Id: Idee966b6434aa038e54b6e7176749a7b65bdbe84 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Do not export function dt_get_stdout_node_offset() that is used only inside stm32mp_dt.c source file. Change-Id: I9dd3dbfab21d42ed81c68723e71fe5a7586dce93 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Correct SDMMC macros to define unsigned values as expected by the driver implementation. Change-Id: Ib009f3df2cf26a9759d129eb571a27b2564770ce Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Remove inclusion of libfdt source files in source file list since these are already included from generic libfdt.mk makefile. Change-Id: If42624557c4d88ca85d70f83b1b08c58f50afe72 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
The system configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. The SYSCFG driver is in charge of configuring masters on the interconnect, IO compensation, low voltage boards, or pull-ups for boot pins. All other configurations should be handled in Linux drivers requiring it. Device tree files are also updated to manage vdd-supply regulator. Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
GPIOx clocks are specific to each STM32MP platforms. This change moves function stm32_get_gpio_bank_clock() from stm32mp common source files to platform private stm32mp1_private.c source file. Change-Id: I9616c0d3fe4d10af715d6f2d1550c13ab62c829a Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Those functions are generic for parsing nodes from device tree hence could be located in generic source file. The oscillators description structure is also moved to STM32MP1 clock driver, as it is no more used in stm32mp1_clkfunc and cannot be in a generic file. Change-Id: I93ba74f4eea916440fef9b160d306af1b39f17c6 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 13 Jun, 2019 1 commit
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Marek Vasut authored
Convert the R-Car Gen3 platform and both SCIF and Log drivers to multi-console API. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I18556973937d150b60453f9150d54ee612571e35
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- 11 Jun, 2019 1 commit
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Louis Mayencourt authored
BL2U should not build when RESET_TO_SP_MIN flag is set, like BL1 and BL2. Change-Id: Iac516121f98611ca1f58d2b5efdec6525b06ce4e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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- 08 Jun, 2019 1 commit
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Samuel Holland authored
As all Allwinner platforms are single-cluster A53 chips, we can disable support for newer, unsupported architecture extensions. We can also avoid some cache maintenance code, since no platform-specific setup is required to enable coherency. These changes reduce the size of .text on a default build with GCC 9.1 enough that .vectors again fits in the second half of a page, instead of requiring its own page. This commit was boot-tested on the Pinebook. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ib90454ef0c798d5e714b7780c585be0b1ed49c6d
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- 06 Jun, 2019 4 commits
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Andrew F. Davis authored
We previously left our caches on during power-down to prevent any non-caching accesses to memory that is cached by other cores. Now with the last accessed areas all being marked as non-cached by USE_COHERENT_MEM we can rely on that to workaround our interconnect issues. Remove the old workaround. Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7 Signed-off-by: Andrew F. Davis <afd@ti.com>
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Andrew F. Davis authored
HW_ASSISTED_COHERENCY implies something stronger than just hardware coherent interconnect, specifically a DynamIQ capable ARM core. For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early and then let the caches get shut off on powerdown, to prevent data corruption we also need to USE_COHERENT_MEM so that any accesses to shared memory after this point is only to memory that is set as non-cached for all cores. Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949 Signed-off-by: Andrew F. Davis <afd@ti.com>
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kenny liang authored
add mcsi driver to support cache coherence. Change-Id: I94f5922783e5dbc6b7e92aa06464bc1f0177f00a Signed-off-by: kenny liang <kenny.liang@mediatek.com>
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kenny liang authored
Add Mediatek GIC driver to support interrupt functions. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I967a18f2e45b7bbc88c506dd4f1f40a745227ad9
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- 05 Jun, 2019 1 commit
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John Tsichritzis authored
During the secondary cores' cold boot path, the cores initialise the GIC CPU interface. However this is a redundant action since 1) the cores are powered down immediately after that, 2) the GIC CPU interface is initialised from scratch when the secondary cores are powered up again later. Moreover, this part of code was introducing a bug. In a GICv3 system, the GIC's CPU interface system registers must not be written without the core being marked as "awake" in the redistributor. However, this sequence was performing such accesses and this would cause those cores to hang. The hang was caused by the DSB instruction that would never complete because of the GIC not recognising those writes. For the two aforementioned reasons, the entire part of the GIC CPU interface initialisation is removed. Change-Id: I6c33a1edda69dd5b6add16a27390a70731b5532a Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 04 Jun, 2019 1 commit
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John Tsichritzis authored
Some cores support only AArch64 mode. In those cores, only a limited subset of the AArch32 system registers are implemented. Hence, if TF-A is supposed to run on AArch64-only cores, it must be compiled with CTX_INCLUDE_AARCH32_REGS=0. Currently, the default settings for compiling TF-A are with the AArch32 system registers included. So, if we compile TF-A the default way and attempt to run it on an AArch64-only core, we only get a runtime panic. Now a compile-time check has been added to ensure that this flag has the appropriate value when AArch64-only cores are included in the build. Change-Id: I298ec550037fafc9347baafb056926d149197d4c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 29 May, 2019 1 commit
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Heiko Stuebner authored
In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are currently imported into special BL31_RO_* constants while the general code also imports them as BL_CODE_BASE and BL_CODE_END. So we can just use the general symbols and can drop the duplication. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d
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- 22 May, 2019 2 commits
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Andrew F. Davis authored
The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a
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Nishanth Menon authored
Enable Cortex-A72 support for J721E. Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
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- 21 May, 2019 1 commit
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Jacky Bai authored
AIPSTZ provide access control for all the peripherals connected to it. In this patch all the perperals are configured accessible to all the master. it can be customized based the actual use case. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I5ef5baa1da6906f13a60923d27ede336c61e319a
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- 20 May, 2019 2 commits
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Leonard Crestez authored
Platform defines are already provided by the build system so let's not duplicate them. Change-Id: Icf1ea76c3c3213e27b447c95e2b22b961fa7693e Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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Leonard Crestez authored
The manual documents that 0x3036006c should contains the soc revision for imx8mq but this always reports A0. Work around this by parsing the ROM header and checking if OCOTP register 0x40 is stuck at 0xff0055aa. Determining this inside TF-A makes life easier for OS, see for example this linux discussion: https://lkml.org/lkml/2019/5/3/465 The soc revision can also be useful inside TF-A itself, for example for the non-upstream DDR DVFS "busfreq" feature is affected by 8mq erratas. The clock for OCOTP block can be disabled by OS so only initialize soc revision once at boot time. Change-Id: I9ca3f27840229ce8a28b53870e44da29f63c73aa Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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