1. 03 Jan, 2020 1 commit
    • Vishnu Banavath's avatar
      drivers: add a driver for snoop control unit · c20c0525
      Vishnu Banavath authored
      
      
      The SCU connects one to four Cortex-A5/Cortex-A9 processors
      to the memory system through the AXI interfaces.
      
      The SCU functions are to:
      - maintain data cache coherency between the Cortex-A5/Cortex-A9
        processors
      - initiate L2 AXI memory accesses
      - arbitrate between Cortex-A5/Cortex-A9 processors requesting
        L2 accesses
      - manage ACP accesses.
      
      Snoop Control Unit will enable to snoop on other CPUs caches.
      This is very important when it comes to synchronizing data between
      CPUs. As an example, there is a high chance that data might be
      cache'd and other CPUs can't see the change. In such cases,
      if snoop control unit is enabled, data is synchoronized immediately
      between CPUs and the changes are visible to other CPUs.
      
      This driver provides functionality to enable SCU as well as enabling
      user to know the following
      - number of CPUs present
      - is a particular CPU operating in SMP mode or AMP mode
      - data cache size of a particular CPU
      - does SCU has ACP port
      - is L2CPRESENT
      
      Change-Id: I0d977970154fa60df57caf449200d471f02312a0
      Signed-off-by: default avatarVishnu Banavath <vishnu.banavath@arm.com>
      c20c0525
  2. 23 Sep, 2019 2 commits
    • Usama Arif's avatar
      a5ds: add multicore support · ec885bac
      Usama Arif authored
      
      
      Enable cores 1-3 using psci. On receiving the smc call from kernel,
      core 0 will bring the secondary cores out pen and signal an event for
      the cores. Currently on switching the cores is enabled i.e. it is not
      possible to suspend, switch cores off, etc.
      
      Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f
      Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      ec885bac
    • Usama Arif's avatar
      a5ds: Hold the secondary cpus in pen rather than panic · e231f3a5
      Usama Arif authored
      
      
      For the secondary CPUs, hold the cpu in wfe rather then panic.
      This will be needed when multicore support is added to a5ds as
      the smc call will write to the hold base and signal an event to
      power on the secondary CPUs.
      
      Change-Id: I0ffc2059e9ef894c21375ca5c94def859bfa6599
      Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      e231f3a5
  3. 16 Jul, 2019 1 commit
    • Usama Arif's avatar
      plat/arm: Introduce A5 DesignStart platform. · 00c7d5ac
      Usama Arif authored
      
      
      This patch adds support for Cortex-A5 FVP for the
      DesignStart program. DesignStart aims at providing
      low cost and fast access to Arm IP.
      
      Currently with this patch only the primary CPU is booted
      and the rest of them wait for an interrupt.
      Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
      00c7d5ac