- 16 Jan, 2020 2 commits
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Hadi Asyrafi authored
This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d
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Hadi Asyrafi authored
SiP CONFIG_ISDONE now will query status for either CONFIG_STATUS or RECONFIG_STATUS based on passed parameter Signed-off-by:
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- 15 Jan, 2020 1 commit
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Hadi Asyrafi authored
All function in socfpga_sip_svc.c should only be called locally except sip_smc_handler(). Signed-off-by:
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- 30 Dec, 2019 1 commit
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Hadi Asyrafi authored
Enable access to secure registers by non-secure world through secure monitor calls Signed-off-by:
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- 17 Dec, 2019 5 commits
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Hadi Asyrafi authored
Fix FPGA reconfiguration driver logic Signed-off-by: -
Hadi Asyrafi authored
Mailbox driver now handles variable response length Signed-off-by: -
Tien Hock, Loh authored
Fixes the SiP Service driver that is responsible for FPGA reconfiguration. Also change the base address of FPGA reconfiguration to 0x400000. Signed-off-by:Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8
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Hadi Asyrafi authored
Move the get_config_status out of sip_svc driver. Modify the function so that it can return either CONFIG_STATUS or RECONFIG_STATUS Signed-off-by: -
Hadi Asyrafi authored
Separate SiP related definition from mailbox header file Signed-off-by:
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- 28 Nov, 2019 2 commits
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Hadi Asyrafi authored
Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: -
Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by:
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 26 Feb, 2019 1 commit
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Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by:
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