- 27 Oct, 2020 4 commits
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch is used to fix remaining non compliant code for Intel SoCFPGA's mailbox and sip driver. These changes include: - Change non-interface required uint32_t into unsigned int - Change non-negative variable to unsigned int - Remove obsolete variable initialization to 0 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5
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Chee Hong Ang authored
Attempt to restart the mailbox if the mailbox driver not able to write any data into the mailbox command buffer. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: Ia45291c985844dec9da82839cac701347534d32b
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch factorizes mailbox read response from SDM into a function. Also fix the logic to support reading larger than 16 words response from SDM. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch modifies several basic mailbox driver features to prepare for FCS enablement: - Job id management for asynchronous response - SDM command buffer full Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2
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- 24 Oct, 2020 3 commits
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Abdul Halim, Muhammad Hadi Asyrafi authored
Sort and rearrange definitions in both mailbox and sip header to increase readability and maintainability. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856
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Abdul Halim, Muhammad Hadi Asyrafi authored
Remove urgent argument from asynchrounous mailbox command as any urgent command should always be synchronous Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319
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Abdul Halim, Muhammad Hadi Asyrafi authored
Use pre-defined macros for return values and common mailbox arguments Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e
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- 25 Feb, 2020 1 commit
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch comes as fixes for 'intel: Fix Coverity Scan Defects' patch. Revert changing argument type from uint32_t to uint64_t to fix incompatible cast issue. Fix said bug by using intermediate uint32_t array as a more appropriate solution. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I344cdabd432cf0a0389b225c934b35d12f4c631d
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- 20 Feb, 2020 1 commit
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Abdul Halim, Muhammad Hadi Asyrafi authored
Fix mailbox driver incompatible cast bug and control flow issue that was flagged by Coverity Scan. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065
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- 05 Feb, 2020 1 commit
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Hadi Asyrafi authored
Introduce support for RSU that can be initiated through SMC calls. Added features as below: - RSU status - RSU update - RSU HPS notify - RSU get sub-partition Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c
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- 16 Jan, 2020 1 commit
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Hadi Asyrafi authored
Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0
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- 17 Dec, 2019 5 commits
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Hadi Asyrafi authored
Mailbox driver now handles variable response length Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic96854fdaadaf48379c5de688392df974e1c99c3
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Hadi Asyrafi authored
Modify mailbox config return code to improve debugging. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0a223291f4c5296203b3295a679a5857a446c692
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Tien Hock, Loh authored
There are a few issues in mailbox that needs to be fixed. - Send doorbell after an indirect cmd - Do not ring doorbell when polling mailbox response as it should've been sent by send_cmd - remove unneeded cmd_free_offset check - Fix mailbox initialization - Fix get_config_status returning a wrong status when the status is busy - Add command length in mailbox command header Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: If613e2ca889a540a616c62d69ad0086a7cd46536
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Hadi Asyrafi authored
Move the get_config_status out of sip_svc driver. Modify the function so that it can return either CONFIG_STATUS or RECONFIG_STATUS Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642d5900339e67f98be61380edc2b838e0dd47af
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Hadi Asyrafi authored
Separate SiP related definition from mailbox header file Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4
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- 28 Nov, 2019 1 commit
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Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
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- 24 Jul, 2019 1 commit
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Ambroise Vincent authored
"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eb ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
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- 11 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 26 Feb, 2019 1 commit
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Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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