- 20 Jan, 2020 7 commits
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Lionel Debieve authored
Add QSPI support (limited to read interface). Implements the memory map and indirect modes. Low level driver based on SPI-MEM operations. Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
Add fmc2_nand driver support. The driver implements only read interface for NAND devices. Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
Device size could be more than 4GB, we must define size as unsigned long long. Change-Id: I52055cf5c1c15ff18ab9e157aa9b73c8b4fb7b63 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
SPI-NOR framework is based on SPI-MEM framework using spi_mem_op execution interface. It implements read functions and allows NOR configuration up to quad mode. Default management is 1 data line but it can be overridden by platform. It also includes specific quad mode configuration for Spansion, Micron and Macronix memories. Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
This framework supports SPI-NAND and is based on the SPI-MEM framework for SPI operations. It uses a common high level access using the io_mtd. It is limited to the read functionalities. Default behavior is the basic one data line operation but it could be overridden by platform. Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
This framework supports SPI operations using a common spi_mem_op structure: - command - addr - dummy - data The framework manages SPI bus configuration: - speed - bus width (Up to quad mode) - chip select Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
The raw NAND framework supports SLC NAND devices. It introduces a new high level interface (io_mtd) that defines operations a driver can register to the NAND framework. This interface will fill in the io_mtd device specification: - device_size - erase_size that could be used by the io_storage interface. NAND core source file integrates the standard read loop that performs NAND device read operations using a skip bad block strategy. A platform buffer must be defined in case of unaligned data. This buffer must fit to the maximum device page size defined by PLATFORM_MTD_MAX_PAGE_SIZE. The raw_nand.c source file embeds the specific NAND operations to read data. The read command is a raw page read without any ECC correction. This can be overridden by a low level driver. No generic support for write or erase command or software ECC correction. NAND ONFI detection is available and can be enabled using NAND_ONFI_DETECT=1. For non-ONFI NAND management, platform can define required information. Change-Id: Id80e9864456cf47f02b74938cf25d99261da8e82 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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- 10 Jan, 2020 1 commit
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Yann Gautier authored
IO seek offset can be set to values above UINT32_MAX, this change changes the seek offset argument from 'ssize_t' to 'signed long long'. Fixing platform seek functions to match the new interface update. Change-Id: I25de83b3b7abe5f52a7b0fee36f71e60cac9cfcb Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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- 03 Jan, 2020 1 commit
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Vishnu Banavath authored
The SCU connects one to four Cortex-A5/Cortex-A9 processors to the memory system through the AXI interfaces. The SCU functions are to: - maintain data cache coherency between the Cortex-A5/Cortex-A9 processors - initiate L2 AXI memory accesses - arbitrate between Cortex-A5/Cortex-A9 processors requesting L2 accesses - manage ACP accesses. Snoop Control Unit will enable to snoop on other CPUs caches. This is very important when it comes to synchronizing data between CPUs. As an example, there is a high chance that data might be cache'd and other CPUs can't see the change. In such cases, if snoop control unit is enabled, data is synchoronized immediately between CPUs and the changes are visible to other CPUs. This driver provides functionality to enable SCU as well as enabling user to know the following - number of CPUs present - is a particular CPU operating in SMP mode or AMP mode - data cache size of a particular CPU - does SCU has ACP port - is L2CPRESENT Change-Id: I0d977970154fa60df57caf449200d471f02312a0 Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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- 30 Dec, 2019 1 commit
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Andre Przywara authored
On some platforms the UART might have already been initialised, for instance by firmware running before TF-A or by a separate management processor. In this case it would not be need to initialise it again (doing so could create spurious characters). But more importantly this saves us from knowing the right baudrate and the right base clock rate for the UART. This can lead to more robust and versatile firmware builds. Allow to skip the 16550 UART initialisation and baud rate divisor programming, by interpreting an input clock rate of "0" to signify this case. This will just skip the call to console_16550_core_init, but still will register the console properly. Users should just pass 0 as the second parameter, the baudrate (third parameter) will then be ignored as well. Fix copy & paste typos in comments for the console_16550_register() function on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I9f8fca5b358f878fac0f31dc411358fd160786ee
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- 14 Dec, 2019 2 commits
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Samuel Holland authored
Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely independent. However, some H6 boards also need early regulator setup. Most of the register interface and all of the device tree traversal code can be reused between the AXP803 and AXP805. The main difference is the hardware bus interface, so that part is left to the platforms. The remainder is moved into a driver. I factored out the bits that were obviously specific to the AXP803; additional changes for compatibility with other PMICs can be made as needed. The only functional change is that rsb_init() now checks the PMIC's chip ID register against the expected value. This was already being done in the H6 version of the code. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2
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Samuel Holland authored
This adds the new regulator list, as well as changes to make the switch (equivalent to DC1SW on the AXP803) work on both PMICs. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I9a1eac8ddfc54b27096c10a8eebdd51aaf9b8311
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- 11 Dec, 2019 1 commit
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Gilad Ben-Yossef authored
Add the support needed to enable using CryptoCell integration with with RSA 3K support. Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com> Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17
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- 11 Nov, 2019 1 commit
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Vijayenthiran Subramaniam authored
Add support to configure GIC-600's multichip routing table registers. Introduce a new gic600 multichip structure in order to support platforms to pass their GIC-600 multichip information such as routing table owner, SPI blocks ownership. This driver is currently experimental and the driver api may change in the future. Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 08 Oct, 2019 1 commit
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Yann Gautier authored
The function has to use read_cntpct_el0() to update the counter, and not read_cntfrq_el0(). Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 03 Oct, 2019 2 commits
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Lionel Debieve authored
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT. timeout_init_us(some_timeout_us); returns a reference to detect timeout for the provided microsecond delay value from current time. timeout_elapsed(reference) return true/false whether the reference timeout is elapsed. Cherry picked from OP-TEE implementation [1]. [1] commit 33d30a74502b ("core: timeout detection support") Minor: - Remove stm32mp platform duplicated implementation. - Add new include in marvell ble.mk Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
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Yann Gautier authored
Use size_t for length parameter in header file, as in .c file. Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 26 Sep, 2019 1 commit
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Madhukar Pappireddy authored
This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU. The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations. Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 20 Sep, 2019 2 commits
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Lionel Debieve authored
This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I1f70ed48a446860498ed111acce01187568538c9
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Lionel Debieve authored
The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585
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- 18 Sep, 2019 1 commit
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Haojian Zhuang authored
The block size of some storage device is 4096-byte long, such as UFS. But PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3
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- 13 Sep, 2019 2 commits
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Andre Przywara authored
To allow sharing the driver between the RPi3 and RPi4, move the random number generator driver into the generic driver directory. Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
To allow sharing the driver between the RPi3 and RPi4, move the mailbox driver into the generic driver directory. Change-Id: I463e49acf82b02bf004f3d56482b7791f3020bc0 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 12 Sep, 2019 1 commit
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Justin Chadwell authored
Previously, TF-A could not support large RSA key sizes as the configuration options passed to MBEDTLS prevented storing and performing calculations with the larger, higher-precision numbers required. With these changes to the arguments passed to MBEDTLS, TF-A now supports using 3072 (3K) and 4096 (4K) keys in certificates. Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 05 Sep, 2019 2 commits
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Carlo Caione authored
The SHA256 DMA driver can be used by multiple SoCs. Move it to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5
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Carlo Caione authored
Meson is the internal code name for the SoC family. The correct name for the platform should be Amlogic. Change the name of the platform directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
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- 04 Sep, 2019 1 commit
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Masahiro Yamada authored
The #include "mbedtls/check_config.h" directive first searches for the header in the relative path to mbedtls_config.h, i.e. include/drivers/auth/mbedtls/mbedtls/check_config.h Obviously, it does not exist since check_config.h is located in the mbedtls project. It is more sensible to use #include <...> form. Change-Id: If72a71381f84e7748a2c9f07dd1176559d9bb1d2 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 02 Sep, 2019 2 commits
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Yann Gautier authored
If the max-frequency property is provided in the device tree mmc node, it should be managed. The max allowed frequency will be the min between this property value and what the card can support. Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Introduce driver for STM32 IWDG peripheral (Independent Watchdog). It is configured according to device tree content and should be enabled from there. The watchdog is not started by default. It can be started after an HW reset if the dedicated OTP is fused. The watchdog also needs to be frozen if a debugger is attached. This is done by configuring the correct bits in DBGMCU. This configuration is allowed by checking BSEC properties. An increase of BL2 size is also required when adding this new code. Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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- 19 Aug, 2019 1 commit
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Masahiro Yamada authored
Currently, console drivers prepend '\r' to '\n' by themselves. This is common enough to be supported in the framework. Add a new flag, CONSOLE_FLAG_TRANSLATE_CRLF. A driver can set this flag to ask the framework to transform LF into CRLF instead of doing it by itself. Change-Id: I4f5c5887591bc0a8749a105abe62b6562eaf503b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 25 Jul, 2019 2 commits
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Gilad Ben-Yossef authored
Add support for multiple Cryptocell revisions which use different APIs. This commit only refactors the existing code in preperation to the addition of another Cryptocell revisions later on. Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com> Change-Id: I16d80b31afb6edd56dc645fee5ea619cc74f09b6
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Gilad Ben-Yossef authored
Code using Cryptocell specific APIs was used as part of the arm common board ROT support, instead of being abstracted in Cryptocell specific driver code, creating two problems: - Any none arm board that uses Cryptocell wuld need to copy and paste the same code. - Inability to cleanly support multiple versions of Cryptocell API and products. Move over Cryptocell specific API calls into the Cryptocell driver, creating abstraction API where needed. Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com> Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e
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- 24 Jul, 2019 1 commit
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Julius Werner authored
This patch adds a new include/export/ directory meant for inclusion in third-party code. This is useful for cases where third-party code needs to interact with TF-A interfaces and data structures (such as a custom BL2-implementation like coreboot handing off to BL31). Directly including headers from the TF-A repository avoids having to duplicate all these definitions (and risk them going stale), but with the current header structure this is not possible because handoff API definitions are too deeply intertwined with other TF code/headers and chain-include other headers that will not be available in the other environment. The new approach aims to solve this by separating only the parts that are really needed into these special headers that are self-contained and will not chain-include other (non-export) headers. TF-A code should never include them directly but should instead always include the respective wrapper header, which will include the required prerequisites (like <stdint.h>) before including the export header. Third-party code can include the export headers via its own wrappers that make sure the necessary definitions are available in whatever way that environment can provide them. Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 12 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 17 Jun, 2019 2 commits
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Yann Gautier authored
Rework the macro that eases the table definition: the src and msk fields are now using MASK and SHIFT defines of each source register. Some macros had then to be modified: _USART1_SEL, _ASS_SEL and _MSS_SEL to _UART1_SEL, _AXIS_SEL, and _MCUS_SEL to match register fields. Note: the mask for RCC_ASSCKSELR_AXISSRC is changed from 0x3 to 0x7 to reflect the size of the register field, even if there are only 3 possible clock sources. The mask value is also corrected for QSPI and FMC clock selection. Change-Id: I44114e3c1dd37b9fa1be1ba519611abd9a07764c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Yann Gautier authored
Those functions are generic for parsing nodes from device tree hence could be located in generic source file. The oscillators description structure is also moved to STM32MP1 clock driver, as it is no more used in stm32mp1_clkfunc and cannot be in a generic file. Change-Id: I93ba74f4eea916440fef9b160d306af1b39f17c6 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 13 Jun, 2019 2 commits
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Marek Vasut authored
Convert the R-Car Gen3 platform and both SCIF and Log drivers to multi-console API. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I18556973937d150b60453f9150d54ee612571e35
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Sandrine Bailleux authored
The chain of trust description and the pointer pointing to its first element were incompatible, thus requiring an explicit type cast for the assignment. - cot_desc was an array of const pointers to const image descriptors. - cot_desc_ptr was a const pointer to (non-constant) pointers to const image descriptors. Thus, trying to assign cot_desc to cot_desc_ptr (with no cast) would generate the following compiler warning: drivers/auth/tbbr/tbbr_cot.c:826:14: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] REGISTER_COT(cot_desc); ^~~~~~~~ Change-Id: Iae62dd1bdb43fe379e3843d96461d47cc2f68a06 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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