- 15 Jan, 2020 6 commits
-
-
Siva Durga Prasad Paladugu authored
The IOU switch clock will be set by PLM during boot so there is no need to set here and hence this patch removes it. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I1512708411eb07a07c1a8fbd66575efee975431a
-
Siva Durga Prasad Paladugu authored
This patch modifies cpu clock for Xilinx Versal virtual platform in order to keep same as used by QEMU. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I169d082462d7ce94a82c62966ab9eb122c5a3fee
-
Tejas Patel authored
Add following APIs in plat_psci to support suspend resume: - versal_pwr_domain_off - versal_pwr_domain_suspend - versal_pwr_domain_suspend_finish - versal_validate_power_state - versal_get_sys_suspend_power_state Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ife908a45f32e2037c9c19e13211a8e4b373b8342
-
Tejas Patel authored
Add support for below suspend related APIs. - self_suspend - abort_suspend - request_suspend Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: If568e0cd33b64754fe66f66fc0cdd0ec62c1b32e
-
Tejas Patel authored
Port ZynqMP PM services for versal to send PM APIs to PMC using IPI. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da
-
Tejas Patel authored
Move versal_def.h to platform specific include directory. Also, update source file to include header file from updated path of versal_def.h Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I313592a17552843b9cc7048f31bcaaefa40ffd91
-
- 04 Jan, 2019 1 commit
-
-
Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 09 Nov, 2018 1 commit
-
-
Siva Durga Prasad Paladugu authored
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. This patch adds Virtual QEMU platform support for this SoC "versal_virt". Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-