- 29 Jan, 2020 1 commit
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Hadi Asyrafi authored
This patch enables uboot's spl entrypoint to BL31 and also handles secondary cpus state during cold boot. Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c
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- 28 Nov, 2019 2 commits
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Hadi Asyrafi authored
Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 30 Jul, 2019 1 commit
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Hadi Asyrafi authored
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by:
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 26 Feb, 2019 1 commit
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Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by:Loh Tien Hock <tien.hock.loh@intel.com>
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