- 17 Oct, 2018 17 commits
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
Signed-off-by: ldts <jramirez@baylibre.com>
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Jorge Ramirez-Ortiz authored
- ddr - pfc [pin function controller] - qos [bandwidth] checkpatch.pl is generating too many errors.
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Jorge Ramirez-Ortiz authored
Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
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- 12 Oct, 2018 1 commit
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Antonio Nino Diaz authored
The comments with the prototypes of the register functions of the console drivers are incorrect. The arguments are wrong. This patch fixes them. Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 11 Oct, 2018 1 commit
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 10 Oct, 2018 2 commits
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Bryan O'Donoghue authored
commit 97d5db8c reverts an update to the MMC layer that accompanied the original submission of this MMC driver this is the right-thing-to-do in terms of the MMC spec. Unfortunately the reversion also breaks this driver. The issue is the i.MX controller doesn't want MMC_RSP_48 set for MMC_RESPONSE_R2. The appropriate place to place that constraint is obviously in drivers/imx/usdhc/imx_usdhc.c not in the shared MMC codebase. This patch restores the logic the i.MX controller requires without breaking it for everyone else. Fixes: 97d5db8c Fixes: 2a82a9c9 Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Jun Nie <jun.nie@linaro.org>
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Antonio Nino Diaz authored
This way it can be reused by other platforms if needed. Note that this driver is designed to work with the Versatile Express NOR flash of Juno and FVP. In said platforms, the memory is organized as an interleaved memory of two chips with a 16 bit word. Any platform that wishes to reuse it with a different configuration will need to modify the driver so that it is more generic. Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 03 Oct, 2018 1 commit
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Daniel Boulby authored
Mark the GICv3, CCI and CCN code only used in Bl31 initialization with __init to be reclaimed once no longer needed. Change-Id: I3d77f36758450d9d1d87ecc60bc1c63fe4082667 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 28 Sep, 2018 8 commits
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Yann Gautier authored
Respect official response type and update response to follow official specification. All the MMC_RESPONSE_R(_x) are replaced with each corresponding define. Partly revert 2a82a9c9 for dw_mmc.c: Responses R1, R1B and R5 have CRC. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Antonio Nino Diaz authored
Change-Id: Icd1cdd42afdc78895a9be6c46b414b0a155cfa63 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
It is still a placeholder, but now it is registered correctly by the macro finish_console_register. Change-Id: Ic78c966d9be606cbc1a53cec43ead23b32963afe Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Ib9eebbdff6f7868e1d1b8c41761cacc7501a25bd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This driver is deprecated. Change-Id: Ic6e154a5756e779743b17a329eed4570ccc61389 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I9874883ec33dbf293f607f9779d7c56f23cb8023 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473 Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Shawn Guo authored
The Poplar is broken on eMMC initialization because of commit 2a82a9c9 ("drivers: emmc: dw_mmc: Add response flag into response ID definition"). It changes the driver behavior on response type handling in dw_send_cmd(), because MMC_RESPONSE_R(2) and MMC_RESPONSE_R2 are different things. MMC core is still sending the former while we already changed to check the latter in dw_mmc driver. This patch fixes R2 response type in MMC core code. It's the same thing as what commit 94522ff7 ("drivers: mmc: Fix R3 response type definition") does for R3 response. With this fix, Poplar is back to work. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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- 25 Sep, 2018 1 commit
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Sathees Balya authored
Change-Id: I43d2b3a0f672b4902edec3d3a39ffedbb0a701a3 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 21 Sep, 2018 2 commits
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Daniel Boulby authored
Allow AArch32 to use the multi console driver by adding the required functions Change-Id: I9e69f18965f320074cf75442d6b0de891aef7936 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Daniel Boulby authored
The old driver is now in deprecated_console.S, in a similar way to the AArch64 driver. Change-Id: Ib57209c322576c451d466d7406a94adbf01ab8fd Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 19 Sep, 2018 1 commit
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Andre Przywara authored
At the moment we have two I2C stub drivers (for the Allwinner and the Marvell platform), which #include the actual .c driver file. Change this into the more usual design, by renaming and moving the stub drivers into platform specific header files and including these from the actual driver file. The platform specific include directories make sure the driver picks up the right header automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 07 Sep, 2018 2 commits
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Icenowy Zheng authored
Allwinner 64-bit SoCs all use the Mentor Graphics MI2CV I2C controller core, with inverted clear quirk. Add a glue driver for this. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Icenowy Zheng authored
The I2C controller on Allwinner SoCs after A31 has a inverted interrupt clear flag, which needs to be written 1 (rather than 0 on Marvell SoCs and old Allwinner SoCs) to clear. Add such a quirk to mi2cv driver common code. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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- 05 Sep, 2018 2 commits
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Icenowy Zheng authored
The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which is also used by Allwinner. As Mentor Graphics allows a lot of customization, the MI2CV in the two SoC families are not compatible, and driver modifications are needed. Extract the common code to a MI2CV driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Icenowy Zheng authored
The I2C controller found in Marvell A8K SoCs (and some older SoCs) mux status and baudrate registers into the same address, however, it's a vendor customization, and the original IP core by Mentor Graphics uses two different addresses for the two registers. Use anonymous union in the driver, in order to ease code sharing for other SoC vendors that use this IP core (Allwinner SoCs that are newly introduced to mainline ATF use this core). Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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- 04 Sep, 2018 2 commits
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Jun Nie authored
Add USDHC driver to support boot EMMC. Only initialization and single/multiple block read are tested. [bod: fixed checkpatch.pl complaints] [bod: changed name to imx_usdhc for namespace consistency] [bod: squashed antecedent fixes into this one patch] Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
Add missing response type for SWITCH command and STOP_TRANSMISSION so that controller can be configured accordingly. [bod: ported this change from Jun's eMMC patches to the MMC driver] Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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