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  1. 22 Mar, 2020 1 commit
  3. 19 Mar, 2020 2 commits
  5. 11 Mar, 2020 2 commits
    • Varun Wadekar's avatar
      Tegra: smmu: export handlers to read/write SMMU registers · 91dd7edd
      Varun Wadekar authored 
      

This patch exports the SMMU register read/write handlers for platforms.

Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      91dd7edd
    • Pritesh Raithatha's avatar
      Tegra: smmu: remove context save sequence · a391d494
      Pritesh Raithatha authored 
      

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      a391d494
  7. 09 Mar, 2020 2 commits
  9. 05 Mar, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra: spe: use CONSOLE_T_BASE to save MMIO base address · 9e7e9867
      Varun Wadekar authored 
      Commit ac71344e

 moved the base address
for the MMIO aperture of the console inside the console_t struct. As
a result, the driver should now save the MMIO base address to console_t
at offset marked by the CONSOLE_T_BASE macro.

This patch updates the SPE console driver to use the CONSOLE_T_BASE macro
to save/access the MMIO base address.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I42afc2608372687832932269108ed642f218fd40
      9e7e9867
  11. 03 Mar, 2020 1 commit
  13. 25 Feb, 2020 1 commit
  15. 20 Feb, 2020 6 commits
    • Varun Wadekar's avatar
      Tegra: spe: uninit console on a timeout · 8a47fe43
      Varun Wadekar authored 
      

There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmware to respond indefinitely.
The console driver must detect such scenarios and uninit the
interface as a result.

This patch adds a timeout to the interaction with the SPE
firmware and uninits the interface if it times out.

Change-Id: I06f27a858baed25711d41105b4110865f1a01727
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8a47fe43
    • Varun Wadekar's avatar
      Tegra: handler to check support for System Suspend · 5d52aea8
      Varun Wadekar authored 
      

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5d52aea8
    • Varun Wadekar's avatar
      Tegra: bpmp_ipc: improve cyclomatic complexity · 21368290
      Varun Wadekar authored 
      

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

    complexity < 10 is accepted
    10 <= complexity < 20 has to be justified
    complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'ipc_send_req_atomic'
handler to reduce the McCabe Cyclomatic Complexity for this function

Change-Id: I20fef79a771301e1c824aea72a45ff83f97591d5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      21368290
    • Varun Wadekar's avatar
      Tegra: platform handler to relocate BL32 image · 6f47acdb
      Varun Wadekar authored 
      

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.

Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      6f47acdb
    • Varun Wadekar's avatar
      Tegra: common: improve cyclomatic complexity · ee21281a
      Varun Wadekar authored 
      

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

    complexity < 10 is accepted
    10 <= complexity < 20 has to be justified
    complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'bl31_early_platform_setup'
handler to reduce the McCabe Cyclomatic Complexity for this function.

Change-Id: Ifb628e33269b388f9323639cd97db761a7e049c4
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ee21281a
    • Varun Wadekar's avatar
      Tegra: delay_timer: support for physical secure timer · dd4f0885
      Varun Wadekar authored 
      

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.

This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.

Change-Id: I2c00f8cb4c48b25578971c626c314603906ad7cc
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      dd4f0885
  17. 31 Jan, 2020 6 commits
    • Varun Wadekar's avatar
      Tegra: bpmp: fix multiple MISRA issues · 64aa08fb
      Varun Wadekar authored 
      

This patch fixes violations for the following MISRA rules

* Rule 5.7  "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.3 "The value of an expression shall not be assigned to an object
             with a narrower essential type or of a different essential type
             category"
* Rule 10.4 "Both operands of an operator in which the usual arithmetic
             conversions are performed shall have the same essential type
             category"
* Rule 20.7 "Expressions resulting from the expansion of macro parameters
             shall be enclosed in parentheses"
* Rule 21.1 "#define and #undef shall not be used on a reserved identifier
             or reserved macro name"

Change-Id: I83cbe659c2d72e76dd4759959870b57c58adafdf
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      64aa08fb
    • Varun Wadekar's avatar
      Tegra: compile PMC driver for Tegra132/Tegra210 platforms · 57c539f9
      Varun Wadekar authored 
      

The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platform specific makefiles.

As a result, the PMC code from common code has been moved to Tegra132
and Tegra210 platform ports.

Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      57c539f9
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler · f561a179
      Varun Wadekar authored 
      

This patch removes the per-platform, weakly defined TZDRAM setup handler,
as all affected platforms implement the actual handler.

Change-Id: I95d04b2a771bc5d673e56b097d45c493fa388ee8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      f561a179
    • Varun Wadekar's avatar
      Tegra: remove weakly defined per-platform SiP handler · ba37943d
      Varun Wadekar authored 
      

This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition.

Change-Id: Id4c7e69163d2635de1813f5a385ac874253a8da9
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ba37943d
    • Varun Wadekar's avatar
      Tegra: remove weakly defined PSCI platform handlers · e44f86ef
      Varun Wadekar authored 
      

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e44f86ef
    • Varun Wadekar's avatar
      Tegra: remove weakly defined platform setup handlers · 39171cd0
      Varun Wadekar authored 
      

This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some MISRA defects.

The weakly defined handlers never get executed thus resulting in
lower coverage - function, function calls, statements, branches
and pairs.

Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      39171cd0
  19. 28 Jan, 2020 1 commit
    • Madhukar Pappireddy's avatar
      Enable -Wredundant-decls warning check · ca661a00
      Madhukar Pappireddy authored 
      

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      ca661a00
  21. 23 Jan, 2020 1 commit
  23. 18 Dec, 2019 1 commit
    • Varun Wadekar's avatar
      Tegra: prepare boot parameters for Trusty · 2783205d
      Varun Wadekar authored 
      This patch saves the boot parameters provided by the previous bootloader
during cold boot and passes them to Trusty. Commit 06ff251e

 introduced
the plat_trusty_set_boot_args() handler, but did not consider the boot
parameters passed by the previous bootloader. This patch fixes that
anomaly.

Change-Id: Ib40dcd02b67c94cea5cefce09edb0be4a998db37
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2783205d
  25. 17 Dec, 2019 1 commit
  27. 28 Nov, 2019 1 commit
    • Varun Wadekar's avatar
      Tegra: introduce plat_enable_console() · 117dbe6c
      Varun Wadekar authored 
      

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      117dbe6c
  29. 24 Oct, 2019 1 commit
  31. 05 Sep, 2019 1 commit
  33. 15 Aug, 2019 1 commit
  35. 20 Jun, 2019 2 commits
  37. 03 Apr, 2019 1 commit
  39. 01 Mar, 2019 1 commit
    • Varun Wadekar's avatar
      Tegra: dummy support for the io_storage backend · 8d56e24b
      Varun Wadekar authored 
      

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8d56e24b
  41. 05 Feb, 2019 3 commits
  43. 31 Jan, 2019 3 commits