- 17 Dec, 2019 1 commit
-
-
Hadi Asyrafi authored
This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3
-
- 12 Dec, 2019 1 commit
-
-
Hadi Asyrafi authored
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by:
-
- 28 Nov, 2019 5 commits
-
-
Hadi Asyrafi authored
Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: -
Hadi Asyrafi authored
Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: -
Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: -
Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
-
- 12 Sep, 2019 2 commits
-
-
Hadi Asyrafi authored
Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: -
Hadi Asyrafi authored
Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by:
-
- 19 Aug, 2019 2 commits
-
-
Hadi Asyrafi authored
Driver will calculate DDR size instead of using hardcoded value Signed-off-by: -
Hadi Asyrafi authored
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by:
-
- 15 Aug, 2019 1 commit
-
-
Hadi Asyrafi authored
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by:
-
- 14 Aug, 2019 1 commit
-
-
Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by:
-
- 13 Aug, 2019 1 commit
-
-
Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by:
-
- 07 Aug, 2019 1 commit
-
-
Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:
-
- 02 Aug, 2019 1 commit
-
-
Hadi Asyrafi authored
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by:
-
- 01 Aug, 2019 1 commit
-
-
Hadi Asyrafi authored
Pull out common code from agilex and stratix10 Signed-off-by:
-
- 30 Jul, 2019 1 commit
-
-
Hadi Asyrafi authored
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by:
-
- 24 Jul, 2019 1 commit
-
-
Ambroise Vincent authored
"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eb ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by:
Ambroise Vincent <ambroise.vincent@arm.com>
-
- 17 Jul, 2019 1 commit
-
-
Hadi Asyrafi authored
Signed-off-by:
-
- 11 Jul, 2019 1 commit
-
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by:Justin Chadwell <justin.chadwell@arm.com>
-
- 10 Jul, 2019 1 commit
-
-
Tien Hock, Loh authored
MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by:Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a
-
- 28 Jun, 2019 1 commit
-
-
Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by:
-
- 26 Jun, 2019 4 commits
-
-
Hadi Asyrafi authored
Signed-off-by: -
Hadi Asyrafi authored
Signed-off-by: -
Hadi Asyrafi authored
Signed-off-by: -
Hadi Asyrafi authored
Signed-off-by:
-
- 21 Mar, 2019 1 commit
-
-
Muhammad Hadi Asyrafi Abdul Halim authored
Watchdog driver support & enablement during platform setup Signed-off-by:
-
- 13 Mar, 2019 2 commits
-
-
Muhammad Hadi Asyrafi Abdul Halim authored
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: -
Muhammad Hadi Asyrafi Abdul Halim authored
To support the enablement of QSPI booting Signed-off-by:
-
- 08 Mar, 2019 2 commits
-
-
Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: -
Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by:
-
- 07 Mar, 2019 2 commits
-
-
Muhammad Hadi Asyrafi Abdul Halim authored
Change map region for device 2 from non-secure to secure Signed-off-by: -
Tien Hock, Loh authored
We should be using zeromem to scrub memory instead of memset. This would improve the performance by 200x Signed-off-by:
-
- 26 Feb, 2019 1 commit
-
-
Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by:
-
- 13 Feb, 2019 1 commit
-
-
Loh Tien Hock authored
A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by:
-
- 04 Feb, 2019 1 commit
-
-
Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by:
-
