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  1. 10 Jul, 2021 3 commits
    • Marek Vasut's avatar
      fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0 · 21924f24
      Marek Vasut authored 
      

The DRAM channel 0 memory area in 32bit space is limited to 2 GiB window.
Furthermore, the first 128 MiB of this memory window are reserved and not
accessible by the system software, hence the 32bit area memory node is
limited to range 0x4800_0000..0xbfff_ffff.

In case there are more than 2 GiB of DRAM populated in channel 0, it is
necessary to generate two memory nodes, once covering the 2 GiB - 128 MiB
area in the 32bit space, and another covering the rest of the memory in
64bit space. This patch implements handling of such a case.
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I3495241fb938e355352e817afaca8f01d04c81d2
      21924f24
    • Marek Vasut's avatar
      refactor(plat/rcar3): factor out DT memory node generation · e624e98d
      Marek Vasut authored 
      

Move the code that adds single new memory@ node into the DT fragment passed
to system software into separate function. Adjust the failure message to be
more specific and print the address range of node which failed to be added.
No functional change.
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie42cd7756b045271f070bca93c524fff6238f5a2
      e624e98d
    • Marek Vasut's avatar
      feat(plat/rcar3): add optional support for gzip-compressed BL33 · ddf2ca03
      Marek Vasut authored 
      

The BL33 size on this platform is limited to 1 MiB, add optional
support for decompressing and starting gzip-compressed BL33, which
may help with this size limitation. This functionality is disabled
by default, set RCAR_GEN3_BL33_GZIP=1 during build to enable it.

The BL33 at 0x50000000 should then be gzip compressed, however if
the BL33 does not have a valid gzip header, it is copied to the
correct location and started as-is, this is a fallback for legacy
systems and systems which update to gzip-compressed BL33.
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id93f1c7e6f17db1ffb952ea086562993473f6efa
      ddf2ca03
  3. 02 Jul, 2021 5 commits
  5. 30 Jun, 2021 2 commits
  7. 29 Jun, 2021 2 commits
    • Sandrine Bailleux's avatar
      refactor(plat/fvp): tidy up list of images to measure · 64dd1dee
      Sandrine Bailleux authored 
      

We don't ever expect to load a binary with an STM32 header on the Arm
FVP platform so remove this type of image from the list of
measurements.

Also remove the GPT image type from the list, as it does not get
measured. GPT is a container, just like FIP is. We don't measure the FIP
but rather the images inside it. It would seem logical to treat GPT the
same way.

Besides, only images that get loaded through load_auth_image() get
measured right now. GPT processing happens before that and is handled in
a different way (see partition_init()).

Change-Id: Iac4de75380ed625b228e69ee4564cf9e67e19336
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      64dd1dee
    • Manish Pandey's avatar
      feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1 · 7285fd5f
      Manish Pandey authored 
      For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14b

Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
      7285fd5f
  9. 28 Jun, 2021 2 commits
  11. 22 Jun, 2021 3 commits
  13. 17 Jun, 2021 2 commits
  15. 15 Jun, 2021 5 commits
  17. 14 Jun, 2021 1 commit
    • Michal Simek's avatar
      feat(plat/zynqmp): extend DT description by TF-A · 0a8143dd
      Michal Simek authored 
      

In case of TF-A running out of DDR there is a need to reserved
memory to let other SW know that none can't use this memory. HW
wise this region can be (and should be) also protected by
protection unit XMPU. This is the first step to add reserved
memory location to DT.

DT address corresponds with default address in U-Boot and also
default address in Xilinx BSPs.

Code is valid only when TF-A runs out of DDR. When it runs out
of OCM there is no need to reseve anything because OCM is hidden
to OS.

Change-Id: I01f230ced67207a159128cc11d11d36dd4590cab
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      0a8143dd
  19. 12 Jun, 2021 2 commits
  21. 04 Jun, 2021 3 commits
  23. 03 Jun, 2021 5 commits
  25. 02 Jun, 2021 2 commits
    • Yann Gautier's avatar
      fix(plat/arm): correct UUID strings in FVP DT · 748bdd19
      Yann Gautier authored 
      

The UUID strings used in FW_CONFIG DT are not aligned with UUIDs defined
in include/tools_share/firmware_image_package.h for BL32_EXTRA1 and
TRUSTED_KEY_CERT.
Signed-off-by: default avatarYann Gautier <yann.gautier@foss.st.com>
Change-Id: I517f8f9311585931f2cb931e0588414da449b694
      748bdd19
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART parent clock rate determination · 5a91c439
      Pali Rohár authored 
      

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
      5a91c439
  27. 01 Jun, 2021 3 commits