GitLab

Adding support for QTI CHIP SC7180 on ATF

Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Co-authored-by: Maulik Shah <mkshah@codeaurora.org>

Change-Id: If82aaba9f2a5a74cfb5e4381f968166037a70037
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE))
to rationalize to an absolute path every time and remove the relative
path assumptions.

This patch also adds documentation that BUILD_BASE can be specified by
the user.
Signed-off-by: Grant Likely <grant.likely@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8

These broken links were found with the help of this command:
$> sphinx-build -M linkcheck . build

A sample broken link is reported as follows:
(line   80) -local-   firmware-design.rst#secure-el1-payloads-and-dispatchers

Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

- Add basic platform setup
- Add mt8192 documentation at docs/plat/
- Add generic CPU helper functions
- Add basic register address

Change-Id: Ife34622105404a8227441aab939e3c55c96374e9
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>

Provide manifest and build options to boot OP-TEE as a
guest S-EL1 Secure Partition on top of Hafnium in S-EL2.

Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb

Openssl directory path is hardcoded to '/usr' in the makefile
of certificate generation and firmware encryption tool using
'OPENSSL_DIR' variable.

Hence changes are done to make 'OPENSSL_DIR' variable as
a build option so that user can provide openssl directory
path while building the certificate generation and firmware
encryption tool.

Also, updated the document for this newly created build option

Change-Id: Ib1538370d2c59263417f5db3746d1087ee1c1339
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

The link to the exception handling framework page on the System Design /
Firmware Design / Section 4.3 just links to itself, so I changed it to
link to the exception handling framework component document.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I6711b423a789b2b3d1921671e8497fffa8ba33d1

Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally
returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to
be not correct for the platform which doesn't implement soc-id
functionality i.e. functions to retrieve both soc-version and
soc-revision.
Hence introduced a platform function which will check whether SMCCC
feature is available for the platform.

Also, updated porting guide for the newly added platform function.

Change-Id: I389f0ef6b0837bb24c712aa995b7176117bc7961
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

This reverts commit 11af40b6, reversing
changes made to 2afcf1d4.

This errata workaround did not work as intended so we are reverting this
change.  In the future, when the corrected workaround is published in an
SDEN, we will push a new workaround.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97

Update SGI-575, RD-E1-Edge and RD-N1-Edge FVP versions to 11.10/36 and
add RD-N1-Edge-Dual to the list of supported Arm Fixed Virtual
Platforms.

Change-Id: I9e7e5662324eeefc80d799ca5341b5bc4dc39cbb
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

This patch adds support for Measured Boot functionality
to FVP platform code. It also defines new properties
in 'tpm_event_log' node to store Event Log address and
it size
'tpm_event_log_sm_addr'
'tpm_event_log_addr'
'tpm_event_log_size'
in 'event_log.dtsi' included in 'fvp_tsp_fw_config.dts'
and 'fvp_nt_fw_config.dts'. The node and its properties
are described in binding document
'docs\components\measured_boot\event_log.rst'.

Change-Id: I087e1423afcb269d6cfe79c1af9c348931991292
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

definitions
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I1c5cc8af34c02a6294ffc44a26152fb8984927fc

Former EL3 Secure Partition Manager using MM protocol is renamed
Secure Partition Manager (MM).
A new Secure Partition Manager document covers TF-A support for the
PSA FF-A compliant implementation.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9763359c2e96181e1726c8ad72738de293b80eb4

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Ib327bda239bb5163c60764bae90b0739589dcf66

This patch adds the following models
 FVP_Base_Neoverse-E1x1
 FVP_Base_Neoverse-E1x2
 FVP_Base_Neoverse-E1x4
to the list of supported FVP platforms.

Change-Id: Ib526a2a735f17724af3a874b06bf69b4ca85d0dd
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

docker (container) is another way to build the documentation and fortunately
there is already a docker image (sphinxdoc/sphinx) with sphinx so we can use
it to generate the documentation.

Change-Id: I06b0621cd7509a8279655e828680b92241b9fde4
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I6d3949a971fada5a086b788dbe274f8451fcfc0d

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)

Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core Arm Cortex-A53 cluster and
Cortex-M7 low-power coprocessor, audio digital signal processor, machine
learning and graphics accelerators.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a

Added a build option 'COT_DESC_IN_DTB' to create chain of trust
at runtime using fconf.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I92b257ac4ece8bbf56f05a41d1e4056e2422ab89

Updated the CoT binding document to show chain of trust relationship
with the help of 'authentication method' and 'authentication data'
instead of showing content of certificate and fixed rendering issue
while creating html page using this document.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib48279cfe786d149ab69ddc711caa381a50f9e2b

Fix the version inconsistency in the same file.

I tested QEMU 5.0.0, and it worked for me.

Change-Id: I9d8ca9aae1e413410eb5676927e13ae4aee9fad8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

In my understanding, /dev/vda2 does not exist unless you add
virtio drive to the qemu command line.

The rootfs is already specified by '-initrd rootfs.cpio.gz'.

Change-Id: Ifdca5d4f3819d87ef7e8a08ed870872d24b86370
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

This commit solves the limitation, "No build instructions for
QEMU_EFI.fd and rootfs-arm64.cpio.gz"

Document the steps to build them.

Change-Id: Ic6d895617cf71fe969f4aa9820dad25cc6182023
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Fix all external broken links reported by Sphinx linkcheck tool.

This does not take care of broken cross-references between internal
TF-A documentation files. These will be fixed in a future patch.

Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

There were some links in the file "ras.rst" which were broken, this
patch fixes all the broken links in this file.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I00cf080e9338af5786239a4843cb4c2e0cc9d99d

Updated the porting guide for the usage of received arguments
in BL2 and BL32 setup functions in case of Arm platform.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia83a5607fed999819d25e49322b3bfb5db9425c0

Updated the document for BL1 and BL2 boot flow to capture
below changes made in FCONF

1. Loading of fw_config and tb_fw_config images by BL1.
2. Population of fw_config and tb_fw_config by BL2.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifea5c61d520ff1de834c279ce1759b53448303ba

Neoverse N1 erratum 1800710 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core.  The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.

This errata is explained in this SDEN:
https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6

Cortex A77 erratum 1800714 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core.  The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.

Since this is the first errata workaround implemented for Cortex A77,
this patch also adds the required cortex_a77_reset_func in the file
lib/cpus/aarch64/cortex_a77.S.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad

Captured the increase in firmware configuration area from
4KB to 8kB in memory layout document. Updated the documentation
to provide details about fw_config separately.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifbec443ced479301be65827b49ff4fe447e9109f

All projects under the TrustedFirmware.org project now use the same
security incident process, therefore update the disclosure/vulnerability
reporting information in the TF-A documentation.

------------------------------------------------------------------------
/!\ IMPORTANT /!\

Please note that the email address to send these reports to has changed.
Please do *not* use trusted-firmware-security@arm.com anymore.

Similarly, the PGP key provided to encrypt emails to the security email
alias has changed as well. Please do *not* use the former one provided
in the TF-A source tree. It is recommended to remove it from your
keyring to avoid any mistake. Please use the new key provided on
TrustedFirmware.org from now on.
------------------------------------------------------------------------

Change-Id: I14eb61017ab99182f1c45d1e156b96d5764934c1
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Added a binding document for COT descriptors which is going
to be used in order to create COT desciptors at run-time.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ic54519b0e16d145cd1609274a00b137a9194e8dd

Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core.  The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.

This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493

Cortex A76 erratum 1791580 is a Cat B erratum present in earlier
revisions of the Cortex A76. The workaround is to set a bit in the
implementation defined CPUACTLR2 register, which forces atomic store
operations to write-back memory to be performed in the L1 data cache.

This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925

Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - disabled
by the default.
Add description of LLC_SRAM flag to the build documentation.

Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

This patch adds BRANCH_PROTECTION = 4 'bti' build option
which turns on branch target identification mechanism.

Change-Id: I32464a6b51726a100519f449a95aea5331f0e82d
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Change-Id: I3726f42f8f3de0cd88bd77a0f9d92a710649d18c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.

RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438