- 31 Jan, 2020 2 commits
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Varun Wadekar authored
This patch converts the weakly defined platform setup handlers into actual platform specific handlers to improve code coverage numbers and some MISRA defects. The weakly defined handlers never get executed thus resulting in lower coverage - function, function calls, statements, branches and pairs. Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support upto 32GB DRAM. This patch moves the common DRAM base/end macros to individual Tegra SoC headers to fix this anomaly. Change-Id: I1a9f386b67c2311baab289e726d95cef6954071b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 29 Jan, 2020 2 commits
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Sandrine Bailleux authored
Allows to select the chain of trust to use when the Trusted Boot feature is enabled. This affects both the cert_create tool and the firmware itself. Right now, the only available CoT is TBBR. Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Andrew Walbran authored
This is based on the rpi implementation from https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746 . Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
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- 28 Jan, 2020 3 commits
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Louis Mayencourt authored
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Varun Wadekar authored
This patch enables the config to switch to the console provided by the SPE firmware. Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 27 Jan, 2020 5 commits
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Andrew F. Davis authored
The current message sequence number is accessed both with caches on and off so put this memory in the un-cached coherent section so accesses are consistent and coherency is maintained. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807
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Andrew F. Davis authored
The 'info' structure contained what is only static data for this implementation of TI-SCI. Remove this indirection and remove the struct. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072
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Andrew F. Davis authored
When all cores in a cluster are powered down the parent cluster can be also powered down. When the last core has requested powering down follow by sending the cluster power down sequence to the system power controller firmware. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216
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Andrew F. Davis authored
The core number is called 'core_id' but the processor and device IDs are called 'proc' and 'device'. Rename these to make them less confusing. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I3d7c6dddd7aa37b5dee1aa9689ce31730e9c3b59
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Vijayenthiran Subramaniam authored
The platform topology description of the upcoming Arm's RD platforms have different topology than those listed in the sgi_topology.c file. So instead of adding platform specific topology into existing sgi_topology.c file, those can be added to respective board files. In order to maintain consistency with the upcoming platforms, move the existing platform topology description to respective board files. Change-Id: I4689c7d24cd0c75a3dc234370c34a85c08598abb Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 24 Jan, 2020 20 commits
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Chris Kay authored
As on SGI platforms, SCPI is unsupported on SGM platforms. Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08 Signed-off-by: Chris Kay <chris.kay@arm.com>
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I76f5535f1cbdaf3fc1235cd824111d9afe8f7e1b
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Masahiro Yamada authored
This platform supports multiple SoCs. The next SoC will still keep quite similar architecture, but the memory base will be changed. The ENABLE_PIE improves the maintainability and usability. You can reuse a single set of BL images for other SoC/board without re-compiling TF-A at all. This will also keep the code cleaner because it avoids #ifdef around various base addresses. By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really position-independent now. You can load them anywhere irrespective of their link address. Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h, that is, determined at link-time. On the other hand, BL2_END, BL31_END, and BL32_END are derived from the symbols produced by the linker scripts. So, they are fixed-up at run-time if ENABLE_PIE is enabled. To make it work in a position-indepenent manner, use BL_CODE_BASE and BL_END, both of which are relocatable. Change-Id: Ic179a7c60eb64c5f3024b178690b3ac7cbd7521b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Currently, UNIPHIER_SCP_BASE is hard-coded in uniphier_scp_start(), which is not handy for PIE. Towards the goal of making this really position-independent, pass in image_info->image_base. Change-Id: I88e020a1919c607b1d5ce70b116201d95773bb63 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Currently, the .buffer field in io_block_dev_spec is statically set, which is not handy for PIE. Towards the goal of making this really position-independent, set the buffer length and length in the uniphier_io_block_setup() function. Change-Id: I22b20d7b58d6ffd38f64f967a2820fca4bd7dade Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Currently, uniphier_bl2_mmap hard-codes the memory region needed for loading other images. Towards the goal of making this really position-independent, call mmap_add_dynamic_region() before that region gets accessed. Change-Id: Ieb505b91ccf2483e5f1a280accda564b33f19f11 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Now that various issues in the PIE support have been fixed, this platform can enable ENABLE_PIE. I tested BL2_AT_EL3, BL31, TSP, and all of them worked. Change-Id: Ibc499c6bad30b7f81a42bfa7e435ce25f820bd9c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ia7072d82116b03904c1b3982f37d96347203e621
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I3421336230981d4cda301fa2cef24b94b08353b1
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ib9f97be1972405e54dc9550266f5b8a6a55b93bf
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I460b35f5a4ec47b13d4e811bb20881ce314e9259
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Iad91e99e9d13254de23eb10e5f655253f253cf0d
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Iee98ded027c049d9f12d4bb5888c0496b3251b4e
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7d660d5a9d7e44601353c77e9b6ee4096a277d76
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I624c15d569db477506a74964bc828e1a932181d4
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7aea86891e54522c88af5ff16795a575f9a9322d
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I8b19e833a4e1067e1cfcc9bfaede7854e0e63004
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I327a8a2ab0f0e49bd62f413296c3b326393422b6
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- 23 Jan, 2020 8 commits
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Varun Wadekar authored
This patch removes unused functions from the NVG driver. * nvg_enable_power_perf_mode * nvg_disable_power_perf_mode * nvg_enable_power_saver_modes * nvg_disable_power_saver_modes * nvg_roc_clean_cache * nvg_roc_flush_cache Change-Id: I0387a40dec35686deaad623a8350de89acfe9393 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch updates the NVG interface header file to v6.6. Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
PCIE0R1 security and override registers need to be preserved across system suspend. Adding them to system suspend save register list. Due to addition of above registers, increasing context save memory by 2 bytes. Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Varun Wadekar authored
This patch enables the GPCDMA for all Tegra194 platforms to help accelerate all the memory copy operations. Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
Many simulation/emulation platforms do not support this hardware block leading to SErrors during register accesses. This patch conditionally accesses the registers from this block only on actual Si and FPGA platforms. Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch organizes the platform memory/mmio map, so that the base addresses for the apertures line up in ascending order. This makes it easier for the xlat_tables_v2 library to create mappings for each mmap_add_region call. Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
PCIE0R1 does not program stream IDs, so allow the stream ID to be overriden by the MC. Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Steven Kao authored
The previous bootloader is not able to pass boot params wider than 32-bits due to an oversight in the scratch register being used. A new secure scratch register #75 has been assigned to pass the higher bits. This patch adds support to parse the higher bits from scratch #75 and use them in calculating the base address for the location of the boot params. Scratch #75 format ==================== 31:16 - bl31_plat_params high address 15:0 - bl31_params high address Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80 Signed-off-by: Steven Kao <skao@nvidia.com>
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