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  1. 28 Sep, 2018 3 commits
  3. 24 Sep, 2018 1 commit
  5. 10 Sep, 2018 1 commit
  7. 07 Sep, 2018 1 commit
    • Alexei Fedorov's avatar
      ARM Platforms:Enable non-secure access to UART1 · 2431d00f
      Alexei Fedorov authored 
      

Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial debug
port for WinDbg (or other debugger) connection.

This option is not documented in the user guide, as it is provided as a
convenience for Windows debugging, and not intended for general use.
In particular, enabling non-secure access to the UART might allow
a denial of service attack!

Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: default avatarEvan Lloyd <evan.lloyd@arm.com>
      2431d00f
  9. 04 Sep, 2018 2 commits
  11. 22 Aug, 2018 1 commit
  13. 03 Aug, 2018 5 commits
  15. 26 Jul, 2018 6 commits
    • Sughosh Ganu's avatar
      RAS: SGI: Add flags needed to build components for RAS feature · f29d1828
      Sughosh Ganu authored 
      

Add the various flags that are required to build the components needed
to enable the RAS feature on SGI575 platform. By default, all flags
are set to 0, disabling building of all corresponding components.

Change-Id: I7f8536fba895043ef6e397cc33ac9126cb572132
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      f29d1828
    • Sughosh Ganu's avatar
      RAS: SGI575: Add platform specific RAS changes · 167dae4d
      Sughosh Ganu authored 
      

Add platform specific changes needed to add support for the RAS
feature on SGI575 platform, including adding a mapping for the
CPER buffer being used on SGI575 platform.

Change-Id: I01a982e283609b5c48661307906346fa2738a43b
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      167dae4d
    • Sughosh Ganu's avatar
      RAS: SGI: Add platform handler for RAS interrupts · 485fc954
      Sughosh Ganu authored 
      

Add a platform specific handler for RAS interrupts and configure the
platform RAS interrupts for EL3 handling. The interrupt handler passes
control to StandaloneMM code executing in S-EL0, which populates the
CPER buffer with relevant error information. The handler subsequently
invokes the SDEI client which processes the information in the error
information in the CPER buffer. The helper functions
plat_sgi_get_ras_ev_map and plat_sgi_get_ras_ev_map_size would be
defined for sgi platforms in the subsequent patch, which adds sgi575
specific RAS changes.

Change-Id: I490f16c15d9917ac40bdc0441659b92380108d63
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      485fc954
    • Sughosh Ganu's avatar
      SPM: SGI: Map memory allocated for secure partitions · d9523919
      Sughosh Ganu authored 
      

The secure partition manager reserves chunks of memory which are used
for the S-EL0 StandaloneMM image and the buffers required for
communication between the Non-Secure world with the StandaloneMM
image. Add the memory chunks to relevant arrays for mapping the
regions of memory with corresponding attributes.

Change-Id: If371d1afee0a50ca7cacd55e16aeaca949d5062b
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      d9523919
    • Sughosh Ganu's avatar
      ARM platforms: Allow board specific definition of SP stack base · 2e4a509d
      Sughosh Ganu authored 
      

The SGI platforms need to allocate memory for CPER buffers. These
platform buffers would be placed between the shared reserved memory
and the per cpu stack memory, thus the need to redefine stack base
pointer for these platforms. This patch allows each board in ARM
platform to define the PLAT_SP_IMAGE_STACK_BASE.

Change-Id: Ib5465448b860ab7ab0f645f7cb278a67acce7be9
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      2e4a509d
    • Sughosh Ganu's avatar
      SGI: Include arm_spm_def.h in platform_def.h · d9cc9372
      Sughosh Ganu authored 
      

Include arm_spm_def.h in the platform_def.h file. Without this
inclusion, we get build errors like

In file included from services/std_svc/spm/sp_setup.c:12:0:
services/std_svc/spm/sp_setup.c: In function 'spm_sp_setup':
services/std_svc/spm/sp_setup.c:61:57: error: 'PLAT_SPM_BUF_BASE'
  undeclared (first use in this function)
  write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE);

Now that the platform_def.h includes arm_spm_def.h, remove inclusion
of platform_def.h in arm_spm_def.h to remove the circular dependency.

Change-Id: I5225c8ca33fd8d288849524395e436c3d56daf17
Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      d9cc9372
  17. 20 Jul, 2018 1 commit
  19. 12 Jul, 2018 2 commits
  21. 10 Jul, 2018 4 commits
    • Roberto Vargas's avatar
      Fix MISRA rule 8.4 · 311a1a8e
      Roberto Vargas authored 
      

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
	make DEBUG=1 PLAT=juno SPD=tspd CSS_USE_SCMI_SDS_DRIVER=1 all

Change-Id: Id732c8df12ef3e20903c41b7ab9a9b55341d68ac
Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      311a1a8e
    • Roberto Vargas's avatar
      Fix MISRA rule 8.3 · 0fbb7a4a
      Roberto Vargas authored 
      

Rule 8.3: All declarations of an object or function shall
              use the same names and type qualifiers.

Fixed for:
make DEBUG=1 PLAT=juno SPD=tspd CSS_USE_SCMI_SDS_DRIVER=1 all

Change-Id: Id9dcc6238b39fac6046abc28141e3ef5e7aa998d
Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      0fbb7a4a
    • Roberto Vargas's avatar
      Fix MISRA rule 8.4 · a9b5b4ae
      Roberto Vargas authored 
      

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
	make DEBUG=1 PLAT=juno ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32

Change-Id: I3ac25096b55774689112ae37bdf1222f9a9ecffb
Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      a9b5b4ae
    • Roberto Vargas's avatar
      Fix MISRA rule 8.3 · c96f297f
      Roberto Vargas authored 
      

Rule 8.3: All declarations of an object or function shall
              use the same names and type qualifiers.

Fixed for:
	make DEBUG=1 PLAT=juno ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32

Change-Id: Ia34f5155e1cdb67161191f69e8d1248cbaa39e1a
Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      c96f297f
  23. 23 Jun, 2018 2 commits
  25. 18 Jun, 2018 1 commit
  27. 15 Jun, 2018 3 commits
  29. 12 Jun, 2018 2 commits
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.7 Part 2 · a138f768
      Daniel Boulby authored 
      

Follow convention of shorter names for smaller scope to fix
violations of MISRA rule 5.7

To prevent violation of directive 4.5 having variable name channel
in css_pm_scmi.c not being typographically ambiguous change macro
argument CHANNEL in css_mhu_doorbell.h change argument to _channel
to fit with our convention which is a permitted exception of
directive 4.5 for this project

Rule 5.7: A tag name shall be a unique identifier

Fixed for:
    make LOG_LEVEL=50 PLAT=juno

Change-Id: I147cdb13553e83ed7df19149b282706db115d612
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      a138f768
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.3 Part 5 · ff4e86f9
      Daniel Boulby authored 
      

Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make LOG_LEVEL=50 PLAT=juno

Change-Id: I575fbc96e8267f2b075e88def1f6e3185394613a
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      ff4e86f9
  31. 07 Jun, 2018 1 commit
    • Soby Mathew's avatar
      ARM platforms: Move BL31 below BL2 to enable BL2 overlay · c099cd39
      Soby Mathew authored 
      

The patch changes the layout of BL images in memory to enable
more efficient use of available space. Previously BL31 was loaded
with the expectation that BL2 memory would be reclaimed by BL32
loaded in SRAM. But with increasing memory requirements in the
firmware, we can no longer fit BL32 in SRAM anymore which means the
BL2 memory is not reclaimed by any runtime image. Positioning BL2
below BL1-RW and above BL31 means that the BL31 NOBITS can be
overlaid on BL2 and BL1-RW.

This patch also propogates the same memory layout to BL32 for AArch32
mode. The reset addresses for the following configurations are also
changed :
   * When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode
   * When BL2_AT_EL3=1 for BL2

The restriction on BL31 to be only in DRAM when SPM is enabled
is now removed with this change. The update to the firmware design
guide for the BL memory layout is done in the following patch.

Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      c099cd39
  33. 16 May, 2018 2 commits
  35. 11 May, 2018 1 commit
  37. 01 May, 2018 1 commit
    • Roberto Vargas's avatar
      ARM platforms: Demonstrate mem_protect from el3_runtime · 638b034c
      Roberto Vargas authored 
      

Previously mem_protect used to be only supported from BL2. This is not
helpful in the case when ARM TF-A BL2 is not used. This patch demonstrates
mem_protect from el3_runtime firmware on ARM Platforms specifically
when RESET_TO_BL31 or RESET_TO_SP_MIN flag is set as BL2 may be absent
in these cases. The Non secure DRAM is dynamically mapped into EL3 mmap
tables temporarily and then the protected regions are then cleared. This
avoids the need to map the non secure DRAM permanently to BL31/sp_min.

The stack size is also increased, because DYNAMIC_XLAT_TABLES require
a bigger stack.

Change-Id: Ia44c594192ed5c5adc596c0cff2c7cc18c001fde
Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      638b034c