Skip to content

GitLab

Switch branch/tag
  1. 24 Feb, 2021 1 commit
  3. 05 Feb, 2021 1 commit
  5. 04 Feb, 2021 1 commit
  7. 03 Feb, 2021 4 commits
  9. 29 Jan, 2021 1 commit
    • Madhukar Pappireddy's avatar
      Fix exception handlers in BL31: Use DSB to synchronize pending EA · c2d32a5f
      Madhukar Pappireddy authored 
      For SoCs which do not implement RAS, use DSB as a barrier to
synchronize pending external aborts at the entry and exit of
exception handlers. This is needed to isolate the SErrors to
appropriate context.

However, this introduces an unintended side effect as discussed
in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440


A summary of the side effect and a quick workaround is provided as
part of this patch and summarized here:

The explicit DSB at the entry of various exception vectors in BL31
for handling exceptions from lower ELs can inadvertently trigger an
SError exception in EL3 due to pending asyncrhonouus aborts in lower
ELs. This will end up being handled by serror_sp_elx in EL3 which will
ultimately panic and die.

The way to workaround is to update a flag to indicate if the exception
truly came from EL3. This flag is allocated in the cpu_context
structure. This is not a bullet proof solution to the problem at hand
because we assume the instructions following "isb" that help to update
the flag (lines 100-102 & 139-141) execute without causing further
exceptions.

Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      c2d32a5f
  11. 20 Jan, 2021 1 commit
  13. 18 Jan, 2021 2 commits
    • Pali Rohár's avatar
      marvell: uart: a3720: Fix macro name for 6th bit of Status Register · b8e637f4
      Pali Rohár authored 
      

This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.

6th bit of the Status Register is named TX EMPTY and is set to 1 when both
Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are
empty. It is when all characters were already transmitted.

There is also TX FIFO EMPTY bit in the Status Register which is set to 1
only when THR is empty.

In both console_a3700_core_init() and console_a3700_core_flush() functions
we should wait until both THR and TSR are empty therefore we should check
6th bit of the Status Register.

So current code is correct, just had misleading macro names and comments.
This change fixes this "documentation" issue, fixes macro name for 6th bit
of the Status Register and also updates comments.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3
      b8e637f4
    • Pali Rohár's avatar
      marvell: uart: a3720: Implement console_a3700_core_getc · 74867756
      Pali Rohár authored 
      

Implementation is simple, just check if there is a pending character in
RX FIFO via RXRDY bit of Status Register and if yes, read it from
UART_RX_REG register.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I226b6e336f44f5d0ca8dcb68e49a68e8f2f49708
      74867756
  15. 15 Jan, 2021 1 commit
  17. 13 Jan, 2021 1 commit
  19. 12 Jan, 2021 1 commit
  21. 11 Jan, 2021 1 commit
    • Michal Simek's avatar
      cadence: Change logic in uart driver · 0b3d4273
      Michal Simek authored 
      

Write char if fifo is empty. If this is done like this all chars are
printed. Because origin code just put that chars to fifo and in case of
reset messages were missing.

Before this change chars are put to fifo and only check before adding if
fifo is full. The patch is changing this logic that it is adding char only
when fifo is empty to make sure that in case of reset (by another SW for
example) all chars are printed. Maybe one char can be missed but for IP
itself it is much easier to send just one char compare to full fifo.
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f
      0b3d4273
  23. 14 Dec, 2020 2 commits
  25. 11 Dec, 2020 1 commit
    • Javier Almansa Sobrino's avatar
      Add support for FEAT_MTPMU for Armv8.6 · 0063dd17
      Javier Almansa Sobrino authored 
      

If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.

If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.

This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: default avatarJavier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
      0063dd17
  27. 02 Dec, 2020 1 commit
  29. 30 Nov, 2020 2 commits
  31. 12 Nov, 2020 2 commits
  33. 28 Oct, 2020 1 commit
    • David Horstmann's avatar
      Use constant stack size with RECLAIM_INIT_CODE · 3ed5606b
      David Horstmann authored 
      

Currently, when RECLAIM_INIT_CODE is set, the
stacks are scaled to ensure that the entirety
of the init section can be reclaimed as stack.

This causes an issue in lib/psci/aarch64/psci_helpers.S,
where the stack size is used for cache operations in
psci_do_pwrdown_cache_maintenance(). If the stacks
are scaled, then the PSCI code may fail to invalidate
some of the stack memory before power down.

Resizing stacks is also not good for stability in general,
since code that works with a small number of cores may
overflow the stack when the number of cores is increased.

Change to make every stack be PLATFORM_STACK_SIZE big,
and allow the total stack to be smaller than the
init section.

Any pages of the init section not reclaimed as
stack will be set to read-only and execute-never,
for security.

Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8
Signed-off-by: default avatarDavid Horstmann <david.horstmann@arm.com>
      3ed5606b
  35. 27 Oct, 2020 1 commit
  37. 20 Oct, 2020 1 commit
  39. 15 Oct, 2020 1 commit
  41. 13 Oct, 2020 1 commit
  43. 12 Oct, 2020 2 commits
    • Jimmy Brisson's avatar
      Increase type widths to satisfy width requirements · d7b5f408
      Jimmy Brisson authored 
      

Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:

    bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
    The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
    0x3c0U" (32 bits) is less that the right hand operand
    "18446744073709547519ULL" (64 bits).

This also resolves MISRA defects such as:

    bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
    In the expression "3U << 20", shifting more than 7 bits, the number
    of bits in the essential type of the left expression, "3U", is
    not allowed.

Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.

This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,

    92407e73        and     x19, x19, #0xffffffff

from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.

The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.

Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      d7b5f408
    • Manish V Badarkhe's avatar
      Remove deprecated macro from TF-A code · c959ea78
      Manish V Badarkhe authored 
      

Removed '__ASSEMBLY__' deprecated macro from TF-A code

Change-Id: I9082a568b695acb5b903f509db11c8672b62d9d0
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      c959ea78
  45. 09 Oct, 2020 2 commits
  47. 07 Oct, 2020 1 commit
  49. 05 Oct, 2020 2 commits
  51. 02 Oct, 2020 1 commit
    • Andre Przywara's avatar
      libfdt: Upgrade libfdt source files · 3b456661
      Andre Przywara authored 
      

Update the libfdt source files, the upstream commit is 73e0f143b73d
("libfdt: fdt_strerror(): Fix comparison warning").

This brings us the fixes for the signed/unsigned comparison warnings,
so platforms can enable -Wsign-compare now.

Change-Id: I303d891c82ffea0acefdde27289339db5ac5a289
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      3b456661
  53. 01 Oct, 2020 1 commit
  55. 29 Sep, 2020 2 commits
    • Andre Przywara's avatar
      fdt: Add function to adjust GICv3 redistributor size · 9f7bab42
      Andre Przywara authored 
      

We now have code to detect the CPU topology at runtime, and can also
populate the CPU nodes in a devicetree accordingly. This is used by the
ARM FPGA port, for instance.
But also a GICv3 compatible interrupt controller provides MMIO frames
per core, so the size of this region needs to be adjusted in the DT,
to match the number of cores as well.

Provide a generic function to find the GICv3 interrupt controller in
the DT, then adjust the "reg" entry to match the number of detected
cores. Since the size of the GICR frame per cores differs between
GICv4 and GICv3, this size is supplied as a parameter to the function.
The caller should determine the applicable value by either hardcoding
it or by observing GICR_TYPER.VLPIS.

Change-Id: Ic2a6445c2c5381a36bf24263f52fcbefad378c05
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      9f7bab42
    • Andre Przywara's avatar
      drivers: arm: gicv3: Allow detecting number of cores · 79d89e3d
      Andre Przywara authored 
      

A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
last frame will have the "Last" bit set in its GICR_TYPER register.

For platforms with a topology unknown at build time (the Arm FPGAs, for
instance), we need to learn the number of used cores at runtime, to size
the GICR region in the devicetree accordingly.

Add a generic function that iterates over all GICR frames until it
encounters one with the "Last" bit set. It returns the number of cores
the GICv3 has been configured for.

Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      79d89e3d
  57. 28 Sep, 2020 1 commit