- 23 Jun, 2020 1 commit
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Etienne Carriere authored
Embed Arch Architecture SMCCC services in stm32mp1 SP_MIN. This service is needed by Linux kernel to setup the SMCCC conduit used by its SCMI SMC transport driver. Change-Id: I454a7ef3048a77ab73fff945e8115b60445d5841 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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- 03 Jun, 2020 1 commit
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Etienne Carriere authored
Use ETZPC driver to configure secure aware interfaces to assign them to non-secure world. Sp_min also configures BootROM resources and SYSRAM to assign both to secure world only. Define stm32mp15 SoC identifiers for the platform specific DECPROT instances. Change-Id: I3bec9f47b04bcba3929e4df886ddb1d5ff843089 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 01 Jun, 2020 1 commit
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Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 11 May, 2020 2 commits
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Etienne Carriere authored
New helper functions to get GPIO banks configuration from the FDT. stm32_get_gpio_bank_pinctrl_node() allows stm32mp platforms to differentiate specific GPIO banks when these are defined with a specific path in the FDT. fdt_get_gpio_bank_pin_count() returns the number of pins in a GPIO bank as it depends on the SoC variant. Change-Id: I4481774152b3c6bf35bf986f58e357c2f9c19176 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Relation between GPIO banks and their base address and offset address if platform dependent. This change moves helper functions stm32_get_gpio_bank_base() and stm32_get_gpio_bank_offset() from plat/st/common to plat/st/stm32mp1/. Change-Id: Id3d03e585746aa5509c6fab7d88183a92d561e3f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 28 Apr, 2020 1 commit
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Andre Przywara authored
The device tree parsing code for the STM32 platform is using its own FDT helper functions, some of them being rather generic. In particular the existing fdt_read_uint32_array() implementation is now almost identical to the new generic code in fdt_wrappers.c, so we can remove the ST specific version and adjust the existing callers. Compared to the original ST implementation the new version takes a pointer to the DTB as the first argument, and also swaps the order of the number of cells and the pointer. Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 26 Mar, 2020 4 commits
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Yann Gautier authored
Instead of using dt_get_ddr_size() and withdrawing the secure and shared memory areas, use stm32mp_get_ddr_ns_size() function. Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
DTB and BL32 area should not be set as executable in MMU during BL2 execution, hence set those areas as MT_RO_DATA. Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
A speculative accesses to DDR could be done whereas it was not reachable and could lead to bus stall. To correct this the dynamic mapping in MMU is used. A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute, once DDR access is setup. It is then unmapped and a new mapping DDR is done with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE) load. The disabling of cache during DDR tests is also removed, as now useless. A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done instead. PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32. BL33 max size is also updated to take into account the secure and shared memory areas. Those are used in OP-TEE case. Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This function gets the DDR size from DT, and withdraws (if defined) the sizes of secure DDR and shared memory areas. This function also checks DT values fits the default DDR range. This non-secure memory is available for BL33 and non-secure OS. Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 25 Feb, 2020 6 commits
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Ahmad Fatoum authored
Board Support for the stm32mp1 platform is contained in the device tree, so if we remove hardcoding of board name from the Makefile, we can build the intermediary objects once and generate one new tf-a-*.stm32 binary for every device tree specified. All in one go. With implicit rules implemented, we only need to change the top level target to support multi-image builds on the stm32mp1. Change-Id: I4cae7d32a4c03a3c29c559dc5332e002223902c1 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Ahmad Fatoum authored
Board Support for the stm32mp1 platform is contained in the device tree, so if we remove hardcoding of board name from the Makefile, we can build the intermediary objects once and generate one new tf-a-*.stm32 binary for every device tree specified. All in one go. Prepare for this by employing implicit rules. Change-Id: I5a022a89eb12696cd8cee7bf28ac6be54849901f Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Ahmad Fatoum authored
Doing this allows us in the next commit to use implicit rules (%-patterns) to cover all the images we generate during a stm32mp1 build. Change-Id: Ibde59d10ccce42566f82820117d7fd0d77345e6c Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Ahmad Fatoum authored
The linker script has no board-specific information that necessitates it having a name derived from the board name. Give it a fixed name, so we can later reuse the same linker script for multiple boards. Change-Id: Ie6650f00389f4ab8577ae82a36c620af9c64101e Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Ahmad Fatoum authored
Currently, building TF-A for STM32MP1 triggers a full rebuild, avoid this by removing the .PHONY: specification for the final image and replace it by specifying PHONYness for the targets that don't actually produce file output. This will come in handy in follow-up commits, when implicit rules are introduced, as implicit rule search is skipped for .PHONY targets. Change-Id: Ib9966479032b081a54123b99f889760e85639f19 Fixes: f74cbc93 ("stm32mp1: Link BL2, BL32 and DTB in one binary") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 28 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I3421336230981d4cda301fa2cef24b94b08353b1
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- 20 Jan, 2020 5 commits
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Lionel Debieve authored
STM32MP1 platform is able to boot from SPI-NOR devices. These modifications add this support using the new SPI-NOR framework. Change-Id: I75ff9eba4661f9fb87ce24ced2bacbf8558ebe44 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
STM32MP1 platform is able to boot from SPI-NAND devices. These modifications add this support using the new SPI-NAND framework. Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
STM32MP1 platform is able to boot from raw NAND devices. These modifications add this support using the new raw NAND framework. Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Nicolas Le Bayon authored
For STM32MP1, the address space is 4GB, which can be first divided in 4 parts of 1GB. This LVL1 table is already mapped regardless of MAX_XLAT_TABLES. Fixing typo: Replace Ko to KB. BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables: - a level2 table and a level3 table for identity mapped SYSRAM - a level2 table mapping 2MB of BootROM runtime resources - a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE) Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Nicolas Le Bayon authored
Adds compilation flags to specify which drivers will be embedded in the generated firmware. Change-Id: Ie9decc89c3f26cf17e7148a3a4cf337fd35940f7 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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- 27 Nov, 2019 1 commit
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Lionel Debieve authored
Change the return code in boot_api.h which impacts the authentication result. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I2c3aadb98dd261ae5ad73978fc74a8a8cfa59b82 Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
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- 23 Sep, 2019 1 commit
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Lionel Debieve authored
This commit adds authentication binary support for STM32MP1. It prints the bootrom authentication result if signed image is used and authenticates the next loaded STM32 images. It also enables the dynamic translation table support (PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
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- 20 Sep, 2019 1 commit
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Lionel Debieve authored
This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I1f70ed48a446860498ed111acce01187568538c9
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- 10 Sep, 2019 1 commit
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Yann Gautier authored
The STM32 console driver was pre-pending '\r' before '\n'. It is now managed by the framework with the flag: CONSOLE_FLAG_TRANSLATE_CRLF. Remove the code in driver, and add the flag for STM32MP1. Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 02 Sep, 2019 7 commits
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Yann Gautier authored
The runtime console is only kept in DEBUG configuration. Change-Id: I0447dfcacb9a63a12bcdab7c55584d70c3220e5b Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This change enhances performance and security in BL32 stage. Change-Id: I64df5995fc6b04f6cf42d6a00a6d3d0f602b5407 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This change enables LpDDR3 initialization with PMIC. Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Among the variants of STM32MP, the STM32MP151 is a single Cortex-A7 chip. A function is added to check the part number of the SoC. If it corresponds to STM32MP151A or STM32MP151C, then the chip has a single Cortex-A7. Change-Id: Icac2015c5d03ce0bcb8e99bbaf1ec8ada34be49c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
On STMicroelectronics boards, the board information is stored in OTP. This OTP is described in device tree, in BSEC board_id node. Change-Id: Ieccbdcb048343680faac8dc577b75c67ac106f5b Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
This information is located in DBGMCU registers. Change-Id: I480aa046fed9992e3d9665b1f0520bc4b6cfdf30 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Introduce driver for STM32 IWDG peripheral (Independent Watchdog). It is configured according to device tree content and should be enabled from there. The watchdog is not started by default. It can be started after an HW reset if the dedicated OTP is fused. The watchdog also needs to be frozen if a debugger is attached. This is done by configuring the correct bits in DBGMCU. This configuration is allowed by checking BSEC properties. An increase of BL2 size is also required when adding this new code. Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 17 Jun, 2019 4 commits
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Yann Gautier authored
Change-Id: Idee966b6434aa038e54b6e7176749a7b65bdbe84 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Correct SDMMC macros to define unsigned values as expected by the driver implementation. Change-Id: Ib009f3df2cf26a9759d129eb571a27b2564770ce Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Remove inclusion of libfdt source files in source file list since these are already included from generic libfdt.mk makefile. Change-Id: If42624557c4d88ca85d70f83b1b08c58f50afe72 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
The system configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. The SYSCFG driver is in charge of configuring masters on the interconnect, IO compensation, low voltage boards, or pull-ups for boot pins. All other configurations should be handled in Linux drivers requiring it. Device tree files are also updated to manage vdd-supply regulator. Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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