- 13 Aug, 2021 1 commit
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Pali Rohár authored
Put default ea handler implementation into function plat_default_ea_handler() which just print verbose information and panic, so it can be called also from overwritten / weak function plat_ea_handler() implementation. Replace every custom implementation of printing verbose error message of external aborts in custom plat_ea_handler() functions by a common implementation from plat_default_ea_handler() function. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98
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- 28 Aug, 2020 1 commit
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David Pu authored
In order to make sure SMC call is within 25us, this patch reduces number of RAS errors accessed to 8 at most for each SMC call and takes a input/output parameter to specify in progress RAS error record index. The measured SMC call latency is about 20us under Linux test kernel driver. Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f Signed-off-by: David Pu <dpu@nvidia.com>
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- 12 Jun, 2020 3 commits
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David Pu authored
This patch provides verbose prints for RAS SErrors handled by the firmware, for improved debugging. Change-Id: Iaad8d183054d884f606dc4621da2cc6b2375bcf9 Signed-off-by: David Pu <dpu@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch introduces a function ID to clear all the RAS error records for corrected errors. Per latest requirement, ARM RAS corrected errors will be reported to lower ELs via interrupts and cleared via SMC. This patch provides required function to clear RAS error status. This patch also sets up all required RAS Corrected errors in order to route RAS corrected errors to lower ELs. Change-Id: I554ba1d0797b736835aa27824782703682c91e51 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: David Pu <dpu@nvidia.com>
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David Pu authored
This patch adds all Tegra194 RAS nodes definitions and support to handle all uncorrectable RAS errors. Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9 Signed-off-by: David Pu <dpu@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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