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At early time, the CPU CA73 retention state has been supported on
Hikey960.  Later we found the system has the hang issue and for
resolving this issue Hisilicon released new MCU firmware, but
unfortunately the new MCU firmware has side effect and results in the
CA73 CPU cannot really enter retention state and roll back to WFI state.

After discussion we cannot see the possibility to enable CA73 retention
state anymore on Hikey960, based on this conclusion we should remove
this state supporting from ARM-TF and roll back to WFI state only.  We
will commit one patch to remove CA73 CPU retention state in kernel DT
binding as well.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Kevin Wang <jean.wangtao@linaro.org>
Cc: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>

The patch fb7d32e5

 migrated the CPU
libraries to have unique defines, prefixing them with the CPU name.

This patch migrates the hikey960 platform port to use the A53 specific
defines.

Change-Id: Id76f544b0b236bbd4974ab5ffa1203f073c20021
Signed-off-by: David Cunado <david.cunado@arm.com>

Support BL31 on HiKey960 platform. Implement PSCI.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Support BL1 on HiKey960 platform. When recovery mode is detected,
BL1 loads NS BL1U that flushs images into UFS. When normal boot
mode is detected, BL1 loads BL2.

Fix for https://github.com/ARM-software/tf-issues/issues/486

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1.
So BL2 will be loaded from eMMC into SRAM later.

Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>