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Macro assert(e) request 'e' is a bool type, if useing other
type, MISRA report a "The Essential Type Model" violation,
Add a judgement to fix the defects, if 'e' is not bool type.

Remove unused code [Rule 2.5]
Fix the essential type model violation [Rule 10.6, 10.7]
Use local parameter to raplace function parameter [Rule 17.8]

Change-Id: Ifce932addbb0a4b063ef6b38349d886c051d81c0
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Main fixes:

Add parentheses to avoid implicit operator precedence [Rule 12.1]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used [Rule 17.7]

Bug 200272157

Change-Id: Ic3ab5a3de95aeb6d2265df940f7fb35ea0f19ab0
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

* EKS blob size was not passed by as a boot parameter
  earlier. Its being passed now
* If EKS value sent by bootloader is non-zero
  update the boot parameter from default value to the argument
  passed by bootloader

Change-Id: I65a3091bd2c1c908cc9e81c0aab6489cab02c098
Signed-off-by: Akshay Sharan <asharan@nvidia.com>

This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.

* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4

Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.

Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

- Migrate to bl31_early_platform_setup2().
- Remove references to removed build options.
- Replace zeromem16() by zeromem().
- Use private definition of bl31_params_t.

This is an incomplete migration, the platform doesn't currently compile.

Change-Id: I67fbf2206678be80c3a16692024221a131cec42f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

With commit cf24229e

 ("Run compiler on debug macros for type
checking"), the compiler will now always evaluate INFO() macro
calls, no matter the LOG_LEVEL value. Therefore, any variable
referenced in the macro has to be be defined.

Address this issue by removing the local variable and using the
expression it was assigned directly in the INFO() call.

Change-Id: Iedc23b3538c1e162372e85390881e50718e50bf3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Void pointers have been used to access linker symbols, by declaring an
extern pointer, then taking the address of it. This limits symbols
values to aligned pointer values. To remove this restriction an
IMPORT_SYM macro has been introduced, which declares it as a char
pointer and casts it to the required type.

Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

Fixes tegra build with SPD=trusty. Not tested.

Change-Id: I851a2b00b8b1cc65112b6088980a811d8eda1a99

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupings and where there are headers within #if statements.

Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>

The 'impl' variable is guarded by the symbol DEBUG, but used in an INFO
level print statement. INFO is defined based on LOG_LEVEL. Hence, builds
would fail when
 - DEBUG=0 && LOG_LEVEL>=LOG_LEVEL_INFO with a variable used but not defined
 - DEBUG=1 && LOG_LEVEL<LOG_LEVEL_INFO with a variable defined but not used

Fixing this by guarding impl with the same condition that guards INFO.

Fixes ARM-software/tf-issues#490
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/



Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

This patch fixes the logic used to calculate the end of NS memory
aperture. The functions allows zero sized NS apertures as that is
a valid requirement for some use cases. e.g. VPR resize.

Change-Id: Ie966e0ea2f9c6888d21c38e734003704094b3720
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.

Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch moves the platform delay timer init to early BL31
platform setup, so that platforms can use the udelay/mdelay
routines in the early init code.

Change-Id: I6fe20b76176ea22589539c180c5b6f9d09eda8de
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch stops initialising the same UART console, as a "crash"
console. The normal and the crash consoles use the same UART port
and hence the crash console init function now only checks if the
console is ready to be used.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direct
path to the IRAM, the MC implements AHB redirection during boot to allow
path to IRAM. In this mode, accesses to a programmed memory address aperture
are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
initialized to disable this aperture. Once bootup is complete, we must
program IRAM base/top, thus disabling access to IRAM.

This patch provides functionality to disable this access. The tegra port
calls this new function before jumping to the non-secure world during
cold boot.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables the SEPARATE_CODE_AND_RODATA build flag for all
Tegra platforms, to allow setting proper MMU attributes for the RO
data and the code.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Some platforms might want to keep the uart console disabled
during boot. This patch checks if the platform supports a
console, before calling console_init().

Change-Id: Icc9c59cb979d91fd0a72e4732403b3284bdd2dfc
Signed-off-by: Damon Duan <danield@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes the console_init() from runtime_setup() as we already
initialize it earlier and disables/enables it across "System Suspend".

Change-Id: I992d3ca56ff4797faf83e8d7fa52c0ef3e1c3367
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support to relocate the BL32 image from the NS
memory to TZDRAM during cold boot. The NS memory buffer is
cleared out after the process completes.

Change-Id: I1a033ffe73b8c309449f874d5187708d0a8846d2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch implements handlers which platforms can override to
get the BL31 arguments passed by the previous bootloader.

Change-Id: I6b9628a984644ce1b5de5aa6d7cd890e57241d89
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch returns pointer to the BL32 entrypoint info only if
it is valid.

Change-Id: I71ce3c4626681753c94f3a7bbaa50c26c74874cb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch configures the TZDRAM fence during early platform
setup to allow the memory controller to enable DRAM encryption
before the TZDRAM actually gets used.

Change-Id: I0169ef9dda75699527b4e30c9e617a9036ba1d76
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler would be added in a subsequent change which can be
registered by the platform code.

This patch adds the GIC programming as part of the tegra_gic_setup()
which now takes an array of all the FIQ interrupts to be enabled for
the platform. The Tegra132 and Tegra210 platforms right now do not
register for any FIQ interrupts themselves, but will definitely use
this support in the future.

Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a weak handler for early platform setup which
can be overriden by the soc-specific handlers to perform any
early setup tasks.

Change-Id: I1a7a98d59b2332a3030c6dca5a9b7be977177326
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support to relocate BL3-1 code to BL31_BASE in case
we cold boot to a different address. This is particularly useful to
maintain compatibility with legacy BL2 code.

This patch also checks to see if the image base address matches either
the TZDRAM or TZSRAM base.

Change-Id: I72c96d7f89076701a6ac2537d4c06565c54dab9c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch maps the TZDRAM carveout used by the BL31. In the near
future BL31 would be running from the TZRAM for security and
performance reasons. The only downside to this solution is that
the TZRAM loses its state in System Suspend. So, we map the TZDRAM
carveout that the BL31 would use to save its state before entering
System Suspend.

Change-Id: Id5bda7e9864afd270cf86418c703fa61c2cb095f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch introduces a function to secure the on-chip TZRAM memory. The
Tegra132 and Tegra210 chips do not have a compelling use case to lock the
TZRAM. The trusted OS owns the TZRAM aperture on these chips and so it
can take care of locking the aperture. This might not be true for future
chips and this patch makes the TZRAM programming flexible.

Change-Id: I3ac9f1de1b792ccd23d4ded274784bbab2ea224a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables the runtime console for all Tegra platforms
before exiting BL31. This would enable debug/error prints to be
always displayed on the UART console.

Change-Id: Ic48d61d05b0ab07973d6fc2dc6b68733a42a3f63
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.

This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.

Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds another member, tzdram_base, to the plat_params_from_bl2 struct
in order to store the TZDRAM carveout base address used to load the Trusted OS.
The monitor programs the memory controller with the TZDRAM base and size in order
to deny any accesses from the NS world.

Change-Id: If39b8674d548175d7ccb6525c18d196ae8a8506c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch checks that the pointers to BL3-3 and BL3-2 ep_info
structs are valid before accessing them. Add some INFO prints
in the BL3-1 setup path for early debugging purposes.

Change-Id: I62b23fa870f1b2fb783c8de69aab819f1749d15a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

We have lots of duplicated defines (and comment blocks too).
Move them to include/plat/common/common_def.h.

While we are here, suffix the end address with _END instead of
_LIMIT.  The _END is a better fit to indicate the linker-derived
real end address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

On Tegra SoCs, the TZDRAM contains the BL31 and BL32 images. This patch
uses only the actual memory available for BL31 instead of mapping the
entire TZDRAM.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes the bootargs pointer from the platform params
structure. Instead the bootargs are passed by the BL2 in the
bl32_ep_info struct which is a part of the EL3 params struct.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch introduces the backend required for implementing the delay
timer API. Tegra has an on-chip free flowing us timer which can be
used as the delay timer.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch sets the 'USE_COHERENT_MEM' flag to '0', so that the
coherent memory region will not be included in the memory map.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>